[Beignet] [PATCH] Fix the bug when MOV dst's hstride is not 1 and span 2 registers.

Zhigang Gong zhigang.gong at linux.intel.com
Thu Jan 22 16:04:32 PST 2015


On Thu, Jan 22, 2015 at 11:06:09PM +0800, junyan.he at inbox.com wrote:
> From: Junyan He <junyan.he at linux.intel.com>
> 
> On IVB, the instructions:
>     mov (16) r104.0<2>:uw r126.0<8;8,1>:uw { Align1, H1 }
>     mov (16) r104.1<2>:uw r111.0<8;8,1>:uw { Align1, H1 }
>     mov (16) r106.0<2>:uw r110.0<8;8,1>:uw { Align1, H1 }
>     mov (16) r106.1<2>:uw r109.0<8;8,1>:uw { Align1, H1 }

Nice catch. The root cause is that it breaks the following restrication:

  "When destination spans two registers, the source MUST span two registers."

The previous implementation assumes that the source registers and destination
registers will never break this restrication which is incorrect.

But this patch seems only fix it partially. Please see detail comments as below

> seems just have effect on the first register and have no
> effect on the second register. This cause the bitcast fail.
> 
> Signed-off-by: Junyan He <junyan.he at linux.intel.com>
> ---
>  backend/src/backend/gen_encoder.cpp |    1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/backend/src/backend/gen_encoder.cpp b/backend/src/backend/gen_encoder.cpp
> index 9058e2e..6a7fba1 100644
> --- a/backend/src/backend/gen_encoder.cpp
> +++ b/backend/src/backend/gen_encoder.cpp
> @@ -91,6 +91,7 @@ namespace gbe
>      if (p->curr.execWidth != 16) return false;
>      if (isVectorOfLongs(dst) == true) return true;
>      if (isCrossMoreThan2(dst) == true) return true;
> +    if (dst.hstride > GEN_HORIZONTAL_STRIDE_1 && (dst.type == GEN_TYPE_UW || dst.type == GEN_TYPE_W)) return true;
If the src.hstride is the same as dst.hstride, then it will not break that restrication.

And we may also need to add the same checking into the needToSplitAlu2 and needToSplitCmp, right?

Thanks,
Zhigang Gong.

>  
>      if (src.hstride == GEN_HORIZONTAL_STRIDE_0) return false;
>  
> -- 
> 1.7.9.5
> 
> 
> 
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