[Beignet] [PATCH] Fix the long bitcast post schedule bug.

[Zhigang Gong]

Sigh, another bug caused by the ambiguous selReg() which allow creating a
register with QW family but float type. The selReg need to be fixed in
the future.

Thanks for the patch, will push latter.

On Mon, Jan 26, 2015 at 06:18:03PM +0800, junyan.he at inbox.com wrote:
> From: Junyan He <junyan.he at linux.intel.com>
> 
> The tmp registers are in wrong type of float, which will
> cause the post schedule error.
> 
> Signed-off-by: Junyan He <junyan.he at linux.intel.com>
> ---
>  backend/src/backend/gen_insn_selection.cpp | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/backend/src/backend/gen_insn_selection.cpp b/backend/src/backend/gen_insn_selection.cpp
> index 628fa2f..6aa7e0e 100644
> --- a/backend/src/backend/gen_insn_selection.cpp
> +++ b/backend/src/backend/gen_insn_selection.cpp
> @@ -3623,12 +3623,12 @@ namespace gbe
>          GBE_ASSERT(isInt64); // Must relate to long and char conversion.
>          if (narrowDst) {
>            for (int i = 0; i < wideNum; i++) {
> -            tmp[i] = sel.selReg(sel.reg(FAMILY_QWORD));
> +            tmp[i] = sel.selReg(sel.reg(FAMILY_QWORD), ir::TYPE_U64);
>              sel.UNPACK_LONG(tmp[i], sel.selReg(insn.getSrc(i), srcType));
>            }
>          } else {
>            for (int i = 0; i < wideNum; i++) {
> -            tmp[i] = sel.selReg(sel.reg(FAMILY_QWORD));
> +            tmp[i] = sel.selReg(sel.reg(FAMILY_QWORD), ir::TYPE_U64);
>            }
>          }
>        }
> -- 
> 1.9.1
> 
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