[Beignet] [PATCH 05/19] Backend: Add half to insn selection.
junyan.he at inbox.com
junyan.he at inbox.com
Thu Jun 11 04:24:21 PDT 2015
From: Junyan He <junyan.he at linux.intel.com>
Add half register as src and dst type for insn selection.
The platforms before BDW do not support half type, so
just generate ASSERT. We will not see half type in insn
selection because the query of the platform extension will
disable fp16.
Signed-off-by: Junyan He <junyan.he at linux.intel.com>
---
backend/src/backend/gen_defs.hpp | 2 ++
backend/src/backend/gen_insn_selection.cpp | 29 +++++++++++++++++++++++++----
backend/src/backend/gen_register.hpp | 7 +++++++
3 files changed, 34 insertions(+), 4 deletions(-)
diff --git a/backend/src/backend/gen_defs.hpp b/backend/src/backend/gen_defs.hpp
index cd6b7c8..1ca148c 100644
--- a/backend/src/backend/gen_defs.hpp
+++ b/backend/src/backend/gen_defs.hpp
@@ -252,6 +252,8 @@ enum GenMessageTarget {
#define GEN_TYPE_UL 8
#define GEN_TYPE_L 9
#define GEN_TYPE_HF 10
+#define GEN_TYPE_DF_IMM 10 /* For the double float in imm. */
+#define GEN_TYPE_HF_IMM 11 /* For the half float in imm. */
#define GEN_ARF_NULL 0x00
#define GEN_ARF_ADDRESS 0x10
diff --git a/backend/src/backend/gen_insn_selection.cpp b/backend/src/backend/gen_insn_selection.cpp
index d63c7e3..64a323d 100644
--- a/backend/src/backend/gen_insn_selection.cpp
+++ b/backend/src/backend/gen_insn_selection.cpp
@@ -126,6 +126,7 @@ namespace gbe
case TYPE_U64: return GEN_TYPE_UL;
case TYPE_FLOAT: return GEN_TYPE_F;
case TYPE_DOUBLE: return GEN_TYPE_DF;
+ case TYPE_HALF: return GEN_TYPE_HF;
default: NOT_SUPPORTED; return GEN_TYPE_F;
}
}
@@ -360,7 +361,9 @@ namespace gbe
bool has32X32Mul() const { return bHas32X32Mul; }
void setHas32X32Mul(bool b) { bHas32X32Mul = b; }
bool hasLongType() const { return bHasLongType; }
+ bool hasHalfType() const { return bHasHalfType; }
void setHasLongType(bool b) { bHasLongType = b; }
+ void setHasHalfType(bool b) { bHasHalfType = b; }
bool hasLongRegRestrict() { return bLongRegRestrict; }
void setLongRegRestrict(bool b) { bLongRegRestrict = b; }
void setLdMsgOrder(uint32_t type) { ldMsgOrder = type; }
@@ -738,6 +741,7 @@ namespace gbe
uint32_t currAuxLabel;
bool bHas32X32Mul;
bool bHasLongType;
+ bool bHasHalfType;
bool bLongRegRestrict;
uint32_t ldMsgOrder;
INLINE ir::LabelIndex newAuxLabel()
@@ -779,7 +783,8 @@ namespace gbe
curr(ctx.getSimdWidth()), file(ctx.getFunction().getRegisterFile()),
maxInsnNum(ctx.getFunction().getLargestBlockSize()), dagPool(maxInsnNum),
stateNum(0), vectorNum(0), bwdCodeGeneration(false), currAuxLabel(ctx.getFunction().labelNum()),
- bHas32X32Mul(false), bHasLongType(false), bLongRegRestrict(false), ldMsgOrder(LD_MSG_ORDER_IVB)
+ bHas32X32Mul(false), bHasLongType(false), bHasHalfType(false), bLongRegRestrict(false),
+ ldMsgOrder(LD_MSG_ORDER_IVB)
{
const ir::Function &fn = ctx.getFunction();
this->regNum = fn.regNum();
@@ -2033,6 +2038,7 @@ namespace gbe
Selection8::Selection8(GenContext &ctx) : Selection(ctx) {
this->opaque->setHas32X32Mul(true);
this->opaque->setHasLongType(true);
+ this->opaque->setHasHalfType(true);
}
SelectionChv::SelectionChv(GenContext &ctx) : Selection(ctx) {
@@ -2144,6 +2150,13 @@ namespace gbe
case TYPE_S8: return GenRegister::immw((int8_t)imm.getIntegerValue() * sign);
case TYPE_DOUBLE: return GenRegister::immdf(imm.getDoubleValue() * sign);
case TYPE_BOOL: return GenRegister::immw((imm.getIntegerValue() == 0) ? 0 : -1); //return 0xffff when true
+ case TYPE_HALF: {
+ ir::half hf = imm.getHalfValue();
+ int16_t _sign = negate ? -1 : 1;
+ ir::half hfSign = ir::half::convToHalf(_sign);
+ hf = hf * hfSign;
+ return GenRegister::immh(hf.getVal());
+ }
default: NOT_SUPPORTED; return GenRegister::immuw(0);
}
}
@@ -3179,6 +3192,11 @@ namespace gbe
sel.MOV(GenRegister::retype(dst, GEN_TYPE_F),
GenRegister::immf(imm.asFloatValue()));
break;
+ case TYPE_HALF: {
+ ir::half hf = imm.getHalfValue();
+ sel.MOV(GenRegister::retype(dst, GEN_TYPE_HF), GenRegister::immh(hf.getVal()));
+ break;
+ }
case TYPE_U16: sel.MOV(dst, GenRegister::immuw(imm.getIntegerValue())); break;
case TYPE_S16: sel.MOV(dst, GenRegister::immw(imm.getIntegerValue())); break;
case TYPE_U8: sel.MOV(dst, GenRegister::immuw(imm.getIntegerValue())); break;
@@ -3212,7 +3230,7 @@ namespace gbe
DECL_CTOR(SyncInstruction, 1,1);
};
- INLINE uint32_t getByteScatterGatherSize(ir::Type type) {
+ INLINE uint32_t getByteScatterGatherSize(Selection::Opaque &sel, ir::Type type) {
using namespace ir;
switch (type) {
case TYPE_DOUBLE:
@@ -3230,6 +3248,9 @@ namespace gbe
case TYPE_U8:
case TYPE_S8:
return GEN_BYTE_SCATTER_BYTE;
+ case TYPE_HALF:
+ if (sel.hasHalfType())
+ return GEN_BYTE_SCATTER_WORD;
default: NOT_SUPPORTED;
return GEN_BYTE_SCATTER_BYTE;
}
@@ -3563,7 +3584,7 @@ namespace gbe
BTI bti = getBTI(dag, insn);
const Type type = insn.getValueType();
- const uint32_t elemSize = getByteScatterGatherSize(type);
+ const uint32_t elemSize = getByteScatterGatherSize(sel, type);
bool allConstant = isAllConstant(bti);
if (allConstant) {
@@ -3723,7 +3744,7 @@ namespace gbe
const ir::StoreInstruction &insn = cast<ir::StoreInstruction>(dag.insn);
GenRegister address = sel.selReg(insn.getAddress(), ir::TYPE_U32);
const Type type = insn.getValueType();
- const uint32_t elemSize = getByteScatterGatherSize(type);
+ const uint32_t elemSize = getByteScatterGatherSize(sel, type);
const bool isUniform = sel.isScalarReg(insn.getAddress()) && sel.isScalarReg(insn.getValue(0));
BTI bti = getBTI(dag, insn);
diff --git a/backend/src/backend/gen_register.hpp b/backend/src/backend/gen_register.hpp
index ecb7ff9..4f37e30 100644
--- a/backend/src/backend/gen_register.hpp
+++ b/backend/src/backend/gen_register.hpp
@@ -80,6 +80,7 @@ namespace gbe
case GEN_TYPE_UW:
case GEN_TYPE_W:
case GEN_TYPE_HF:
+ case GEN_TYPE_HF_IMM:
return 2;
case GEN_TYPE_UB:
case GEN_TYPE_B:
@@ -642,6 +643,12 @@ namespace gbe
return immediate;
}
+ static INLINE GenRegister immh(uint16_t uw) {
+ GenRegister immediate = imm(GEN_TYPE_HF_IMM);
+ immediate.value.ud = uw;
+ return immediate;
+ }
+
static INLINE GenRegister immv(uint32_t v) {
GenRegister immediate = imm(GEN_TYPE_V);
immediate.vstride = GEN_VERTICAL_STRIDE_0;
--
1.9.1
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