[Beignet] [PATCH] GBE: support compare two bool variables.

[Gong, Zhigang]

That's the tricky part. And as I know, i1 1 is actually -1 thus is less than 0.
And you can see it is consistent when you extent i1 to i16 which is a signed extend.

> -----Original Message-----
> From: Yang, Rong R
> Sent: Monday, March 2, 2015 4:11 PM
> To: Gong, Zhigang; beignet at lists.freedesktop.org
> Cc: Gong, Zhigang
> Subject: RE: [Beignet] [PATCH] GBE: support compare two bool variables.
> 
> For the instruction:
> %Pivot = icmp slt i1 %trunc49, false
> 
> And slt is: interprets the operands as signed values and yields true if op1 is less
> than op2.
> 
> But %trunc49 only has 1 bit, How to interprets %trunc49 as signed values? Only
> signed bit?
> 
> When %trunc49's value is true, what should be this instruction's result?
> 
> > -----Original Message-----
> > From: Beignet [mailto:beignet-bounces at lists.freedesktop.org] On Behalf
> > Of Zhigang Gong
> > Sent: Monday, March 2, 2015 12:29
> > To: beignet at lists.freedesktop.org
> > Cc: Gong, Zhigang
> > Subject: [Beignet] [PATCH] GBE: support compare two bool variables.
> >
> > LLVM 3.6 may generate the following instructions:
> >
> > %Pivot = icmp slt i1 %trunc49, false
> >
> > when do siwth lowering pass.
> > To support it we must use GEN_TYPE_W to represent B rather than
> > GEN_TYPE_UW and we also need to remove the corresponding assertions.
> >
> > Signed-off-by: Zhigang Gong <zhigang.gong at intel.com>
> > ---
> >  backend/src/backend/gen_insn_selection.cpp | 4 ++--
> >  backend/src/ir/instruction.cpp             | 1 -
> >  backend/src/llvm/llvm_gen_backend.cpp      | 2 --
> >  3 files changed, 2 insertions(+), 5 deletions(-)
> >
> > diff --git a/backend/src/backend/gen_insn_selection.cpp
> > b/backend/src/backend/gen_insn_selection.cpp
> > index 106ea82..d100f80 100644
> > --- a/backend/src/backend/gen_insn_selection.cpp
> > +++ b/backend/src/backend/gen_insn_selection.cpp
> > @@ -115,7 +115,7 @@ namespace gbe
> >    uint32_t getGenType(ir::Type type) {
> >      using namespace ir;
> >      switch (type) {
> > -      case TYPE_BOOL: return GEN_TYPE_UW;
> > +      case TYPE_BOOL: return GEN_TYPE_W;
> >        case TYPE_S8: return GEN_TYPE_B;
> >        case TYPE_U8: return GEN_TYPE_UB;
> >        case TYPE_S16: return GEN_TYPE_W; @@ -1956,7 +1956,7 @@
> > namespace gbe
> >        case TYPE_U8:  return
> GenRegister::immuw(imm.getIntegerValue()
> > * sign);
> >        case TYPE_S8:  return
> > GenRegister::immw((int8_t)imm.getIntegerValue()
> > * sign);
> >        case TYPE_DOUBLE: return
> > GenRegister::immdf(imm.getDoubleValue() * sign);
> > -      case TYPE_BOOL: return
> GenRegister::immuw(-imm.getIntegerValue());
> > //return 0xffff when true
> > +      case TYPE_BOOL: return
> GenRegister::immw((imm.getIntegerValue()
> > + == 0) ? 0 : -1);  //return 0xffff when true
> >        default: NOT_SUPPORTED; return GenRegister::immuw(0);
> >      }
> >    }
> > diff --git a/backend/src/ir/instruction.cpp
> > b/backend/src/ir/instruction.cpp index 1e1b040..a2bc875 100644
> > --- a/backend/src/ir/instruction.cpp
> > +++ b/backend/src/ir/instruction.cpp
> > @@ -889,7 +889,6 @@ namespace ir {
> >        for (uint32_t srcID = 0; srcID < 2; ++srcID)
> >          if (UNLIKELY(checkRegisterData(family, src[srcID], fn, whyNot) ==
> false))
> >            return false;
> > -      CHECK_TYPE(this->type, allButBool);
> >        return true;
> >      }
> >
> > diff --git a/backend/src/llvm/llvm_gen_backend.cpp
> > b/backend/src/llvm/llvm_gen_backend.cpp
> > index 43b50e7..238f572 100644
> > --- a/backend/src/llvm/llvm_gen_backend.cpp
> > +++ b/backend/src/llvm/llvm_gen_backend.cpp
> > @@ -2151,8 +2151,6 @@ namespace gbe
> >    }
> >
> >    void GenWriter::emitICmpInst(ICmpInst &I) {
> > -    GBE_ASSERT(I.getOperand(0)->getType() !=
> > Type::getInt1Ty(I.getContext()));
> > -
> >      // Get the element type and the number of elements
> >      Type *operandType = I.getOperand(0)->getType();
> >      const ir::Type type = getType(ctx, operandType);
> > --
> > 1.9.1
> >
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