[Beignet] [PATCH 5/8] GBE: don't type cast register/labelindex to integer.
Zhigang Gong
zhigang.gong at intel.com
Tue Mar 31 19:05:40 PDT 2015
Signed-off-by: Zhigang Gong <zhigang.gong at intel.com>
---
backend/src/backend/gen_insn_selection.cpp | 52 +++++++++++++++---------------
backend/src/ir/instruction.cpp | 5 ++-
backend/src/ir/register.hpp | 8 ++---
3 files changed, 32 insertions(+), 33 deletions(-)
diff --git a/backend/src/backend/gen_insn_selection.cpp b/backend/src/backend/gen_insn_selection.cpp
index 490525f..27ed11b 100644
--- a/backend/src/backend/gen_insn_selection.cpp
+++ b/backend/src/backend/gen_insn_selection.cpp
@@ -1020,7 +1020,7 @@ namespace gbe
void Selection::Opaque::LABEL(ir::LabelIndex index) {
SelectionInstruction *insn = this->appendInsn(SEL_OP_LABEL, 0, 0);
- insn->index = uint32_t(index);
+ insn->index = index.value();
}
void Selection::Opaque::BARRIER(GenRegister src, GenRegister fence, uint32_t barrierType) {
@@ -1038,7 +1038,7 @@ namespace gbe
int Selection::Opaque::JMPI(Reg src, ir::LabelIndex index, ir::LabelIndex origin) {
SelectionInstruction *insn = this->appendInsn(SEL_OP_JMPI, 0, 1);
insn->src(0) = src;
- insn->index = uint32_t(index);
+ insn->index = index.value();
insn->extra.longjmp = abs(index - origin) > 800;
return insn->extra.longjmp ? 2 : 1;
}
@@ -1046,28 +1046,28 @@ namespace gbe
void Selection::Opaque::BRD(Reg src, ir::LabelIndex jip) {
SelectionInstruction *insn = this->appendInsn(SEL_OP_BRD, 0, 1);
insn->src(0) = src;
- insn->index = uint32_t(jip);
+ insn->index = jip.value();
}
void Selection::Opaque::BRC(Reg src, ir::LabelIndex jip, ir::LabelIndex uip) {
SelectionInstruction *insn = this->appendInsn(SEL_OP_BRC, 0, 1);
insn->src(0) = src;
- insn->index = uint32_t(jip);
- insn->index1 = uint32_t(uip);
+ insn->index = jip.value();
+ insn->index1 = uip.value();
}
void Selection::Opaque::IF(Reg src, ir::LabelIndex jip, ir::LabelIndex uip) {
SelectionInstruction *insn = this->appendInsn(SEL_OP_IF, 0, 1);
insn->src(0) = src;
- insn->index = uint32_t(jip);
- insn->index1 = uint32_t(uip);
+ insn->index = jip.value();
+ insn->index1 = uip.value();
}
void Selection::Opaque::ELSE(Reg src, ir::LabelIndex jip, ir::LabelIndex elseLabel) {
SelectionInstruction *insn = this->appendInsn(SEL_OP_ELSE, 0, 1);
insn->src(0) = src;
- insn->index = uint32_t(jip);
+ insn->index = jip.value();
this->LABEL(elseLabel);
}
@@ -1079,13 +1079,13 @@ namespace gbe
this->LABEL(this->block->endifLabel);
SelectionInstruction *insn = this->appendInsn(SEL_OP_ENDIF, 0, 1);
insn->src(0) = src;
- insn->index = uint32_t(this->block->endifLabel);
+ insn->index = this->block->endifLabel.value();
}
void Selection::Opaque::WHILE(Reg src, ir::LabelIndex jip) {
SelectionInstruction *insn = this->appendInsn(SEL_OP_WHILE, 0, 1);
insn->src(0) = src;
- insn->index = uint32_t(jip);
+ insn->index = jip.value();
}
void Selection::Opaque::CMP(uint32_t conditional, Reg src0, Reg src1, Reg dst) {
@@ -1687,7 +1687,7 @@ namespace gbe
if (this->ctx.getIFENDIFFix() &&
this->block->insnList.size() != 0 &&
this->block->insnList.size() % 1000 == 0 &&
- (uint32_t)this->block->endifLabel != 0) {
+ this->block->endifLabel.value() != 0) {
ir::LabelIndex jip = this->block->endifLabel;
this->ENDIF(GenRegister::immd(0), jip);
this->push();
@@ -2001,7 +2001,7 @@ namespace gbe
if (sel.getRegisterFamily(insn.getDst(0)) == ir::FAMILY_BOOL &&
dag->isUsed) {
sel.curr.physicalFlag = 0;
- sel.curr.flagIndex = (uint32_t)(insn.getDst(0));
+ sel.curr.flagIndex = insn.getDst(0).value();
sel.curr.modFlag = 1;
}
sel.MOV(dst, src);
@@ -2209,7 +2209,7 @@ namespace gbe
insn.getOpcode() == OP_OR ||
insn.getOpcode() == OP_XOR);
sel.curr.physicalFlag = 0;
- sel.curr.flagIndex = (uint32_t)(insn.getDst(0));
+ sel.curr.flagIndex = insn.getDst(0).value();
sel.curr.modFlag = 1;
}
@@ -2782,7 +2782,7 @@ namespace gbe
if (!sel.isScalarReg(insn.getDst(0)) && sel.regDAG[insn.getDst(0)]->isUsed) {
sel.curr.modFlag = 1;
sel.curr.physicalFlag = 0;
- sel.curr.flagIndex = (uint32_t) insn.getDst(0);
+ sel.curr.flagIndex = insn.getDst(0).value();
}
sel.MOV(dst, imm.getIntegerValue() ? GenRegister::immuw(0xffff) : GenRegister::immuw(0));
break;
@@ -3042,7 +3042,7 @@ namespace gbe
sel.curr.physicalFlag = 0;
sel.curr.modFlag = 1;
sel.curr.predicate = GEN_PREDICATE_NONE;
- sel.curr.flagIndex = (uint32_t)alignedFlag;
+ sel.curr.flagIndex = alignedFlag.value();
sel.CMP(GEN_CONDITIONAL_NEQ, GenRegister::unpacked_uw(shiftHReg), GenRegister::immuw(32));
sel.pop();
@@ -3055,7 +3055,7 @@ namespace gbe
// Only need to consider the tmpH when the addr is not aligned.
sel.curr.modFlag = 0;
sel.curr.physicalFlag = 0;
- sel.curr.flagIndex = (uint32_t)alignedFlag;
+ sel.curr.flagIndex = alignedFlag.value();
sel.curr.predicate = GEN_PREDICATE_NORMAL;
sel.SHL(tmpH, tmp[i + 1], shiftH);
sel.OR(effectData[i], tmpL, tmpH);
@@ -3377,7 +3377,7 @@ namespace gbe
sel.curr.noMask = 1;
sel.curr.physicalFlag = 0;
sel.curr.modFlag = 1;
- sel.curr.flagIndex = (uint32_t)dst;
+ sel.curr.flagIndex = dst.value();
sel.curr.grfFlag = needStoreBool; // indicate whether we need to allocate grf to store this boolean.
if (type == TYPE_S64 || type == TYPE_U64) {
GenRegister tmp[3];
@@ -3791,7 +3791,7 @@ namespace gbe
}
sel.curr.inversePredicate ^= inverse;
sel.curr.physicalFlag = 0;
- sel.curr.flagIndex = (uint32_t) pred;
+ sel.curr.flagIndex = pred.value();
sel.curr.predicate = GEN_PREDICATE_NORMAL;
// FIXME in general, if the flag is a uniform flag.
// we should treat that flag as extern flag, as we
@@ -3914,7 +3914,7 @@ namespace gbe
// FIXME, if the last BRA is unconditional jump, we don't need to update the label here.
sel.push();
sel.curr.predicate = GEN_PREDICATE_NORMAL;
- sel.MOV(GenRegister::retype(src0, GEN_TYPE_UW), GenRegister::immuw((uint16_t)label));
+ sel.MOV(GenRegister::retype(src0, GEN_TYPE_UW), GenRegister::immuw(label.value()));
sel.pop();
}
else {
@@ -4204,9 +4204,9 @@ namespace gbe
// as if there is no backward jump latter, then obviously everything will work fine.
// If there is backward jump latter, then all the pcip will be updated correctly there.
sel.curr.physicalFlag = 0;
- sel.curr.flagIndex = (uint32_t) pred;
+ sel.curr.flagIndex = pred.value();
sel.curr.predicate = GEN_PREDICATE_NORMAL;
- sel.MOV(ip, GenRegister::immuw(uint16_t(dst)));
+ sel.MOV(ip, GenRegister::immuw(dst.value()));
sel.curr.predicate = GEN_PREDICATE_NONE;
if (!sel.block->hasBarrier && !sel.block->removeSimpleIfEndif)
sel.ENDIF(GenRegister::immd(0), nextLabel);
@@ -4216,7 +4216,7 @@ namespace gbe
// Update the PcIPs
const LabelIndex jip = sel.ctx.getLabelIndex(&insn);
if(insn.getParent()->needEndif)
- sel.MOV(ip, GenRegister::immuw(uint16_t(dst)));
+ sel.MOV(ip, GenRegister::immuw(dst.value()));
if (!sel.block->hasBarrier && !sel.block->removeSimpleIfEndif) {
if(insn.getParent()->needEndif && !insn.getParent()->needIf)
@@ -4257,13 +4257,13 @@ namespace gbe
// block. Next instruction will properly update the IPs of the lanes
// that actually take the branch
const LabelIndex next = bb.getNextBlock()->getLabelIndex();
- sel.MOV(ip, GenRegister::immuw(uint16_t(next)));
+ sel.MOV(ip, GenRegister::immuw(next.value()));
GBE_ASSERT(jip == dst);
sel.push();
sel.curr.physicalFlag = 0;
- sel.curr.flagIndex = (uint32_t) pred;
+ sel.curr.flagIndex = pred.value();
sel.curr.predicate = GEN_PREDICATE_NORMAL;
- sel.MOV(ip, GenRegister::immuw(uint16_t(dst)));
+ sel.MOV(ip, GenRegister::immuw(dst.value()));
sel.block->endifOffset = -1;
sel.curr.predicate = GEN_PREDICATE_NONE;
if (!sel.block->hasBarrier && !sel.block->removeSimpleIfEndif)
@@ -4280,7 +4280,7 @@ namespace gbe
const LabelIndex next = bb.getNextBlock()->getLabelIndex();
// Update the PcIPs
if(insn.getParent()->needEndif)
- sel.MOV(ip, GenRegister::immuw(uint16_t(dst)));
+ sel.MOV(ip, GenRegister::immuw(dst.value()));
sel.block->endifOffset = -1;
if (!sel.block->hasBarrier && !sel.block->removeSimpleIfEndif) {
if(insn.getParent()->needEndif && !insn.getParent()->needIf)
diff --git a/backend/src/ir/instruction.cpp b/backend/src/ir/instruction.cpp
index 8bd19b6..583bab5 100644
--- a/backend/src/ir/instruction.cpp
+++ b/backend/src/ir/instruction.cpp
@@ -741,7 +741,7 @@ namespace ir {
const Function &fn,
std::string &whyNot)
{
- if (UNLIKELY(uint32_t(ID) >= fn.regNum())) {
+ if (UNLIKELY(ID.value() >= fn.regNum())) {
whyNot = "Out-of-bound destination register index";
return false;
}
@@ -885,9 +885,8 @@ namespace ir {
return false;
const RegisterFamily family = getFamily(this->type);
for (uint32_t srcID = 0; srcID < 2; ++srcID)
- if (UNLIKELY(checkRegisterData(family, src[srcID], fn, whyNot) == false)) {
+ if (UNLIKELY(checkRegisterData(family, src[srcID], fn, whyNot) == false))
return false;
- }
return true;
}
diff --git a/backend/src/ir/register.hpp b/backend/src/ir/register.hpp
index be5f60d..d8df7b0 100644
--- a/backend/src/ir/register.hpp
+++ b/backend/src/ir/register.hpp
@@ -129,8 +129,8 @@ namespace ir {
public:
/*! Return the index of a newly allocated register */
INLINE Register append(RegisterFamily family, bool uniform = false) {
- GBE_ASSERTM(regNum() < MAX_INDEX,
- "Too many defined registers (only 65535 are supported)");
+ GBE_ASSERTM((uint64_t)regNum() < MAX_INDEX,
+ "Too many defined registers (only 4G are supported)");
const uint32_t index = regNum();
const RegisterData reg(family, uniform);
regs.push_back(reg);
@@ -157,11 +157,11 @@ namespace ir {
INLINE void setUniform(Register index, bool uniform) { regs[index].setUniform(uniform); }
/*! Get the register index from the tuple */
INLINE Register get(Tuple index, uint32_t which) const {
- return regTuples[uint32_t(index) + which];
+ return regTuples[index.value() + which];
}
/*! Set the register index from the tuple */
INLINE void set(Tuple index, uint32_t which, Register reg) {
- regTuples[uint32_t(index) + which] = reg;
+ regTuples[index.value() + which] = reg;
}
/*! Number of registers in the register file */
INLINE uint32_t regNum(void) const { return regs.size(); }
--
1.9.1
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