[Beignet] [PATCH 2/6] Debug Support: Pass debug infomation to context

[Bai Yannan]

    1. Add a new structure DBGInfo into context class, storing debug information.
    2. Pass debug information from llvm IR to Context, for subsequently passing, if OCL_PROFILING is true.

Signed-off-by: Yannan Bai <yannan.bai at intel.com>
Signed-off-by: Meng Lv <meng.lv at intel.com>
---
 backend/src/ir/context.hpp            |  5 +++++
 backend/src/llvm/llvm_gen_backend.cpp | 18 +++++++++++++++++-
 2 files changed, 22 insertions(+), 1 deletion(-)

diff --git a/backend/src/ir/context.hpp b/backend/src/ir/context.hpp
index 0f7ded4..ca576bd 100644
--- a/backend/src/ir/context.hpp
+++ b/backend/src/ir/context.hpp
@@ -209,6 +209,7 @@ namespace ir {
       this->STORE(type, index, offset, space, valueNum, dwAligned, fixedBTI, bti);
     }
     void appendSurface(uint8_t bti, Register reg) { fn->appendSurface(bti, reg); }
+    void setDBGInfo(uint32_t line, uint32_t col) { DBGInfo.line = line; DBGInfo.col = col; }
 
   protected:
     /*! A block must be started with a label */
@@ -233,6 +234,10 @@ namespace ir {
       vector<uint8_t> *usedLabels; //!< Store all labels that are defined
     };
     vector<StackElem> fnStack;     //!< Stack of functions still to finish
+    struct {
+      uint32_t line;
+      uint32_t col;
+    }DBGInfo;
     GBE_CLASS(Context);
   };
 
diff --git a/backend/src/llvm/llvm_gen_backend.cpp b/backend/src/llvm/llvm_gen_backend.cpp
index 3d76265..19088e5 100644
--- a/backend/src/llvm/llvm_gen_backend.cpp
+++ b/backend/src/llvm/llvm_gen_backend.cpp
@@ -83,6 +83,8 @@
 #include "sys/cvar.hpp"
 #include "backend/program.h"
 #include <sstream>
+#include "llvm/IR/DebugLoc.h"
+#include "llvm/IR/DebugInfo.h"
 
 /* Not defined for LLVM 3.0 */
 #if !defined(LLVM_VERSION_MAJOR)
@@ -101,6 +103,7 @@ using namespace llvm;
 
 namespace gbe
 {
+  extern bool OCL_PROFILING; // first defined by calling BVAR in program.cpp
   /*! Gen IR manipulates only scalar types */
   static bool isScalarType(const Type *type)
   {
@@ -638,6 +641,7 @@ namespace gbe
     void emitUnalignedDQLoadStore(ir::Register ptr, Value *llvmValues, ir::AddressSpace addrSpace, ir::Register bti, bool isLoad, bool dwAligned, bool fixedBTI);
     void visitInstruction(Instruction &I) {NOT_SUPPORTED;}
     private:
+      void setDebugInfo_CTX(llvm::Instruction * insn); // store the debug infomation in context for subsequently passing to Gen insn
       ir::ImmediateIndex processConstantImmIndexImpl(Constant *CPV, int32_t index = 0u);
       template <typename T, typename P = T>
       ir::ImmediateIndex processSeqConstant(ConstantDataSequential *seq,
@@ -1745,7 +1749,13 @@ namespace gbe
   void GenWriter::emitBasicBlock(BasicBlock *BB) {
     GBE_ASSERT(labelMap.find(BB) != labelMap.end());
     ctx.LABEL(labelMap[BB]);
-    for (auto II = BB->begin(), E = BB->end(); II != E; ++II) visit(*II);
+    for (auto II = BB->begin(), E = BB->end(); II != E; ++II) {
+      if(OCL_PROFILING) {
+        llvm::Instruction * It = dyn_cast<llvm::Instruction>(II);
+        setDebugInfo_CTX(It);
+      }
+      visit(*II);
+    }
   }
 
   void GenWriter::emitMovForPHI(BasicBlock *curr, BasicBlock *succ) {
@@ -1812,6 +1822,12 @@ namespace gbe
     }
   }
 
+  void GenWriter::setDebugInfo_CTX(llvm::Instruction * insn)
+  {
+    llvm::DebugLoc dg = insn->getDebugLoc();
+    ctx.setDBGInfo(dg.getLine(), dg.getCol());
+  }
+
   void GenWriter::emitFunctionPrototype(Function &F)
   {
     GBE_ASSERTM(F.hasStructRetAttr() == false,
-- 
1.9.1