[Beignet] [PATCH 4/5] GBE/DebugInfo: Pass debug info : SEL IR => GenInsn
Bai Yannan
yannan.bai at intel.com
Mon Nov 16 23:53:12 PST 2015
1. Add a structure DBGInfo in GenEncoder class, storing debug infomation for subsequentlt passing to GenInsn.
2. Add a structure type GenInsnDBGInfo in GenInstruction defination.
3. Add a vector<GenInsnDBGInfo> in GenEncoder class, storing debug information corresponding to vector<GenInstruction>.
4. Pass debug information from SEL IR firstly to Gen Encoder, then pass to Gen Instruction when emitting, if OCL_DEBUGINFO is true.
Signed-off-by: Yannan Bai <yannan.bai at intel.com>
---
backend/src/backend/gen_context.cpp | 8 ++++++++
backend/src/backend/gen_defs.hpp | 6 ++++++
backend/src/backend/gen_encoder.cpp | 16 ++++++++++++++++
backend/src/backend/gen_encoder.hpp | 3 +++
4 files changed, 33 insertions(+)
diff --git a/backend/src/backend/gen_context.cpp b/backend/src/backend/gen_context.cpp
index 9868043..7a122b5 100644
--- a/backend/src/backend/gen_context.cpp
+++ b/backend/src/backend/gen_context.cpp
@@ -92,6 +92,12 @@ namespace gbe
return i;
}
+ extern bool OCL_DEBUGINFO; // first defined by calling BVAR in program.cpp
+#define SET_GENINSN_DBGINFO(I) \
+ if(OCL_DEBUGINFO) { \
+ p->DBGInfo.line = I.DBGInfo.line; \
+ p->DBGInfo.col = I.DBGInfo.col;}
+
void GenContext::emitInstructionStream(void) {
// Emit Gen ISA
for (auto &block : *sel->blockList)
@@ -101,6 +107,7 @@ namespace gbe
// no more virtual register here in that part of the code generation
GBE_ASSERT(insn.state.physicalFlag);
p->curr = insn.state;
+ SET_GENINSN_DBGINFO(insn);
switch (opcode) {
#define DECL_SELECTION_IR(OPCODE, FAMILY) \
case SEL_OP_##OPCODE: this->emit##FAMILY(insn); break;
@@ -114,6 +121,7 @@ namespace gbe
for(int i = 0; i < 8; i++)
p->NOP();
}
+#undef SET_GENINSN_DBGINFO
bool GenContext::patchBranches(void) {
using namespace ir;
diff --git a/backend/src/backend/gen_defs.hpp b/backend/src/backend/gen_defs.hpp
index 09cb2ba..7d45fa7 100644
--- a/backend/src/backend/gen_defs.hpp
+++ b/backend/src/backend/gen_defs.hpp
@@ -490,6 +490,12 @@ struct GenInstruction {
uint32_t high;
};
+/* Structure to store source infomation for each GenInstruction */
+typedef struct _GenInsnDBGInfo {
+ uint32_t srcline;
+ uint32_t srccol;
+} GenInsnDBGInfo;
+
union GenCompactInstruction {
struct GenInstruction low;
struct {
diff --git a/backend/src/backend/gen_encoder.cpp b/backend/src/backend/gen_encoder.cpp
index b153a2c..93f0806 100644
--- a/backend/src/backend/gen_encoder.cpp
+++ b/backend/src/backend/gen_encoder.cpp
@@ -591,11 +591,26 @@ namespace gbe
this->setSrc1(insn, bti);
}
}
+
+ extern bool OCL_DEBUGINFO; // first defined by calling BVAR in program.cpp
+ void GenEncoder::setDBGInfo(DebugInfo in, bool hasHigh)
+ {
+ if(OCL_DEBUGINFO)
+ {
+ GenInsnDBGInfo dginfo;
+ dginfo.srcline = in.line;
+ dginfo.srccol = in.col;
+ storedbg.push_back(dginfo);
+ if(hasHigh) storedbg.push_back(dginfo);
+ }
+ }
+
GenCompactInstruction *GenEncoder::nextCompact(uint32_t opcode) {
GenCompactInstruction insn;
std::memset(&insn, 0, sizeof(GenCompactInstruction));
insn.bits1.opcode = opcode;
this->store.push_back(insn.low);
+ setDBGInfo(DBGInfo, false);
return (GenCompactInstruction *)&this->store.back();
}
@@ -605,6 +620,7 @@ namespace gbe
insn.header.opcode = opcode;
this->store.push_back(insn.low);
this->store.push_back(insn.high);
+ setDBGInfo(DBGInfo, true);
return (GenNativeInstruction *)(&this->store.back()-1);
}
diff --git a/backend/src/backend/gen_encoder.hpp b/backend/src/backend/gen_encoder.hpp
index e9945e8..9210ab3 100644
--- a/backend/src/backend/gen_encoder.hpp
+++ b/backend/src/backend/gen_encoder.hpp
@@ -88,6 +88,9 @@ namespace gbe
uint32_t deviceID;
/*! simd width for this codegen */
uint32_t simdWidth;
+ DebugInfo DBGInfo;
+ vector<GenInsnDBGInfo> storedbg;
+ void setDBGInfo(DebugInfo in, bool hasHigh);
////////////////////////////////////////////////////////////////////////
// Encoding functions
////////////////////////////////////////////////////////////////////////
--
1.9.1
More information about the Beignet
mailing list