[Beignet] [PATCH V3 3/5] GBE/DebugInfo: Pass debug info : GEN IR => SEL IR

[Bai Yannan]

    1. Add a DebugInfo type structure DBGInfo in Opaqueue class, storing debug infomation in selection for subsequentlt passing to selection IR.
    2. Add a DebugInfo type structure DBGInfo in SelectionInstruction class, storing debug infomation.
    3. Pass debug information from GEN IR firstly to selection queue, then pass to selection IR when emitting, if OCL_DEBUGINFO is true.

Signed-off-by: Yannan Bai <yannan.bai at intel.com>
---
 backend/src/backend/gen_insn_selection.cpp | 11 +++++++++++
 backend/src/backend/gen_insn_selection.hpp |  3 +++
 2 files changed, 14 insertions(+)

diff --git a/backend/src/backend/gen_insn_selection.cpp b/backend/src/backend/gen_insn_selection.cpp
index 84cfb6d..9971e20 100644
--- a/backend/src/backend/gen_insn_selection.cpp
+++ b/backend/src/backend/gen_insn_selection.cpp
@@ -458,6 +458,8 @@ namespace gbe
     bool hasQWord(const ir::Instruction &insn);
     /*! A root instruction needs to be generated */
     bool isRoot(const ir::Instruction &insn) const;
+    /*! Set debug infomation to Selection */
+    void setDBGInfo_SEL(DebugInfo in) { DBGInfo = in; }
 
     /*! To handle selection block allocation */
     DECL_POOL(SelectionBlock, blockPool);
@@ -495,6 +497,7 @@ namespace gbe
     uint32_t vectorNum;
     /*! If true, generate code backward */
     bool bwdCodeGeneration;
+    DebugInfo DBGInfo;
     /*! To make function prototypes more readable */
     typedef const GenRegister &Reg;
 
@@ -867,6 +870,7 @@ namespace gbe
     GBE_ASSERT(dstNum <= SelectionInstruction::MAX_DST_NUM && srcNum <= SelectionInstruction::MAX_SRC_NUM);
     GBE_ASSERT(this->block != NULL);
     SelectionInstruction *insn = this->create(opcode, dstNum, srcNum);
+    insn->setDBGInfo(DBGInfo);
     if (this->bwdCodeGeneration)
       this->bwdList.push_back(insn);
     else
@@ -2058,6 +2062,11 @@ namespace gbe
     return insnNum;
   }
 
+extern bool OCL_DEBUGINFO; // first defined by calling BVAR in program.cpp
+#define SET_SEL_DBGINFO(I)  \
+	if(OCL_DEBUGINFO)	 \
+	  sel.setDBGInfo_SEL(I.DBGInfo)
+
   void Selection::Opaque::matchBasicBlock(const ir::BasicBlock &bb, uint32_t insnNum)
   {
     // Bottom up code generation
@@ -2077,6 +2086,7 @@ namespace gbe
     for (int32_t insnID = insnNum-1; insnID >= 0; --insnID) {
       // Process all possible patterns for this instruction
       SelectionDAG &dag = *insnDAG[insnID];
+      SET_SEL_DBGINFO(dag.insn);
       if (dag.isRoot) {
         const ir::Instruction &insn = dag.insn;
         const ir::Opcode opcode = insn.getOpcode();
@@ -2128,6 +2138,7 @@ namespace gbe
       }
     }
   }
+#undef SET_SEL_DBGINFO
 
   void Selection::Opaque::select(void)
   {
diff --git a/backend/src/backend/gen_insn_selection.hpp b/backend/src/backend/gen_insn_selection.hpp
index 32e5ce2..ec45812 100644
--- a/backend/src/backend/gen_insn_selection.hpp
+++ b/backend/src/backend/gen_insn_selection.hpp
@@ -90,6 +90,8 @@ namespace gbe
     const GenRegister &dst(uint32_t dstID) const { return regs[dstID]; }
     /*! Damn C++ */
     const GenRegister &src(uint32_t srcID) const { return regs[dstNum+srcID]; }
+    /*! Set debug infomation to selection */
+    void setDBGInfo(DebugInfo in) { DBGInfo = in; }
     /*! No more than 40 sources (40 sources are used by vme for payload passing and setting) */
     enum { MAX_SRC_NUM = 40 };
     /*! No more than 16 destinations (15 used by I64DIV/I64REM) */
@@ -159,6 +161,7 @@ namespace gbe
     uint32_t index1;
     /*! instruction ID used for vector allocation. */
     uint32_t ID;
+    DebugInfo DBGInfo;
     /*! Variable sized. Destinations and sources go here */
     GenRegister regs[0];
     INLINE uint32_t getbti() const {
-- 
1.9.1