[Beignet] [PATCH 2/4] runtime: refine the cl_device_id to support bigger memory
Pan Xiuli
xiuli.pan at intel.com
Wed Oct 14 01:34:05 PDT 2015
Now gen8 and gen9 support 4G global memory, and gen9 support
4G single buffer. Need to move the global_mem and max_mem_alloc
size into each define header.
Signed-off-by: Pan Xiuli <xiuli.pan at intel.com>
---
src/cl_device_id.c | 14 +++++++-------
src/cl_gen75_device.h | 5 +++--
src/cl_gen7_device.h | 2 ++
src/cl_gen8_device.h | 30 ++++++++++++++++++++++++++++++
src/cl_gen9_device.h | 31 +++++++++++++++++++++++++++++++
src/cl_gt_device.h | 2 --
6 files changed, 73 insertions(+), 11 deletions(-)
create mode 100644 src/cl_gen8_device.h
create mode 100644 src/cl_gen9_device.h
diff --git a/src/cl_device_id.c b/src/cl_device_id.c
index 78d2cf4..d92ce95 100644
--- a/src/cl_device_id.c
+++ b/src/cl_device_id.c
@@ -116,7 +116,7 @@ static struct _cl_device_id intel_brw_gt1_device = {
.max_work_item_sizes = {512, 512, 512},
.max_work_group_size = 512,
.max_clock_frequency = 1000,
-#include "cl_gen75_device.h"
+#include "cl_gen8_device.h"
};
static struct _cl_device_id intel_brw_gt2_device = {
@@ -127,7 +127,7 @@ static struct _cl_device_id intel_brw_gt2_device = {
.max_work_item_sizes = {512, 512, 512},
.max_work_group_size = 512,
.max_clock_frequency = 1000,
-#include "cl_gen75_device.h"
+#include "cl_gen8_device.h"
};
static struct _cl_device_id intel_brw_gt3_device = {
@@ -138,7 +138,7 @@ static struct _cl_device_id intel_brw_gt3_device = {
.max_work_item_sizes = {512, 512, 512},
.max_work_group_size = 512,
.max_clock_frequency = 1000,
-#include "cl_gen75_device.h"
+#include "cl_gen8_device.h"
};
//Cherryview has the same pciid, must get the max_compute_unit and max_thread_per_unit from drm
@@ -162,7 +162,7 @@ static struct _cl_device_id intel_skl_gt1_device = {
.max_work_item_sizes = {512, 512, 512},
.max_work_group_size = 512,
.max_clock_frequency = 1000,
-#include "cl_gen75_device.h"
+#include "cl_gen9_device.h"
};
static struct _cl_device_id intel_skl_gt2_device = {
@@ -173,7 +173,7 @@ static struct _cl_device_id intel_skl_gt2_device = {
.max_work_item_sizes = {512, 512, 512},
.max_work_group_size = 512,
.max_clock_frequency = 1000,
-#include "cl_gen75_device.h"
+#include "cl_gen9_device.h"
};
static struct _cl_device_id intel_skl_gt3_device = {
@@ -184,7 +184,7 @@ static struct _cl_device_id intel_skl_gt3_device = {
.max_work_item_sizes = {512, 512, 512},
.max_work_group_size = 512,
.max_clock_frequency = 1000,
-#include "cl_gen75_device.h"
+#include "cl_gen9_device.h"
};
static struct _cl_device_id intel_skl_gt4_device = {
@@ -195,7 +195,7 @@ static struct _cl_device_id intel_skl_gt4_device = {
.max_work_item_sizes = {512, 512, 512},
.max_work_group_size = 512,
.max_clock_frequency = 1000,
-#include "cl_gen75_device.h"
+#include "cl_gen9_device.h"
};
LOCAL cl_device_id
diff --git a/src/cl_gen75_device.h b/src/cl_gen75_device.h
index 43f6e8f..7ef2b82 100644
--- a/src/cl_gen75_device.h
+++ b/src/cl_gen75_device.h
@@ -17,14 +17,15 @@
* Author: Benjamin Segovia <benjamin.segovia at intel.com>
*/
-/* Common fields for both SNB devices (either GT1 or GT2)
- */
+/* Common fields for both CHV,VLV and HSW devices */
.max_parameter_size = 1024,
.global_mem_cache_line_size = 64, /* XXX */
.global_mem_cache_size = 8 << 10, /* XXX */
.local_mem_type = CL_GLOBAL,
.local_mem_size = 64 << 10,
.scratch_mem_size = 2 << 20,
+.max_mem_alloc_size = 2 * 1024 * 1024 * 1024ul,
+.global_mem_size = 2 * 1024 * 1024 * 1024ul,
#include "cl_gt_device.h"
diff --git a/src/cl_gen7_device.h b/src/cl_gen7_device.h
index 4ad5d96..104e929 100644
--- a/src/cl_gen7_device.h
+++ b/src/cl_gen7_device.h
@@ -24,6 +24,8 @@
.local_mem_type = CL_GLOBAL,
.local_mem_size = 64 << 10,
.scratch_mem_size = 12 << 10,
+.max_mem_alloc_size = 2 * 1024 * 1024 * 1024ul,
+.global_mem_size = 2 * 1024 * 1024 * 1024ul,
#include "cl_gt_device.h"
diff --git a/src/cl_gen8_device.h b/src/cl_gen8_device.h
new file mode 100644
index 0000000..08fde48
--- /dev/null
+++ b/src/cl_gen8_device.h
@@ -0,0 +1,30 @@
+/*
+ * Copyright © 2012 Intel Corporation
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2.1 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library. If not, see <http://www.gnu.org/licenses/>.
+ *
+ * Author: Benjamin Segovia <benjamin.segovia at intel.com>
+ */
+
+/* Common fields for both BDW devices */
+.max_parameter_size = 1024,
+.global_mem_cache_line_size = 64, /* XXX */
+.global_mem_cache_size = 8 << 10, /* XXX */
+.local_mem_type = CL_GLOBAL,
+.local_mem_size = 64 << 10,
+.scratch_mem_size = 2 << 20,
+.max_mem_alloc_size = 2 * 1024 * 1024 * 1024ul,
+.global_mem_size = 4 * 1024 * 1024 * 1024ul,
+
+#include "cl_gt_device.h"
diff --git a/src/cl_gen9_device.h b/src/cl_gen9_device.h
new file mode 100644
index 0000000..f50f9c7
--- /dev/null
+++ b/src/cl_gen9_device.h
@@ -0,0 +1,31 @@
+/*
+ * Copyright © 2012 Intel Corporation
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2.1 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library. If not, see <http://www.gnu.org/licenses/>.
+ *
+ * Author: Benjamin Segovia <benjamin.segovia at intel.com>
+ */
+
+/* Common fields for both SKL devices */
+.max_parameter_size = 1024,
+.global_mem_cache_line_size = 64, /* XXX */
+.global_mem_cache_size = 8 << 10, /* XXX */
+.local_mem_type = CL_GLOBAL,
+.local_mem_size = 64 << 10,
+.scratch_mem_size = 2 << 20,
+.max_mem_alloc_size = 4 * 1024 * 1024 * 1024ul,
+.global_mem_size = 4 * 1024 * 1024 * 1024ul,
+
+#include "cl_gt_device.h"
+
diff --git a/src/cl_gt_device.h b/src/cl_gt_device.h
index 07ead7c..e99475d 100644
--- a/src/cl_gt_device.h
+++ b/src/cl_gt_device.h
@@ -41,7 +41,6 @@
.native_vector_width_half = 8,
.preferred_wg_sz_mul = 32,
.address_bits = 32,
-.max_mem_alloc_size = 512 * 1024 * 1024,
.image_support = CL_TRUE,
.max_read_image_args = BTI_MAX_READ_IMAGE_ARGS,
.max_write_image_args = BTI_MAX_WRITE_IMAGE_ARGS,
@@ -57,7 +56,6 @@
.min_data_type_align_size = sizeof(cl_long) * 16,
.double_fp_config = 0,
.global_mem_cache_type = CL_READ_WRITE_CACHE,
-.global_mem_size = 1024 * 1024 * 1024,
.max_constant_buffer_size = 128 * 1024 * 1024,
.max_constant_args = 8,
.error_correction_support = CL_FALSE,
--
2.1.4
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