[Beignet] [Patch v2 1/4] alignment of NO TILING surface limitation shouldn't be removed.

[xionghu.luo at intel.com]

From: Luo Xionghu <xionghu.luo at intel.com>

it could cause sampler data mismatch on IVB.

Signed-off-by: Luo Xionghu <xionghu.luo at intel.com>
---
 src/cl_mem.c | 7 ++++---
 1 file changed, 4 insertions(+), 3 deletions(-)

diff --git a/src/cl_mem.c b/src/cl_mem.c
index 561e0a4..dd5078e 100644
--- a/src/cl_mem.c
+++ b/src/cl_mem.c
@@ -847,10 +847,11 @@ _cl_mem_new_image(cl_context ctx,
   /* Tiling requires to align both pitch and height */
   if (tiling == CL_NO_TILE) {
     aligned_pitch = w * bpp;
-    if(image_type == CL_MEM_OBJECT_IMAGE1D_ARRAY || image_type == CL_MEM_OBJECT_IMAGE2D_ARRAY)
-      aligned_h  = ALIGN(h, cl_buffer_get_tiling_align(ctx, CL_NO_TILE, 1));
-    else
+    //no need align the height if 2d image from buffer.
+    if (image_type == CL_MEM_OBJECT_IMAGE2D && buffer != NULL)
       aligned_h = h;
+    else
+      aligned_h  = ALIGN(h, cl_buffer_get_tiling_align(ctx, CL_NO_TILE, 1));
   } else if (tiling == CL_TILE_X) {
     aligned_pitch = ALIGN(w * bpp, cl_buffer_get_tiling_align(ctx, CL_TILE_X, 0));
     aligned_h     = ALIGN(h, cl_buffer_get_tiling_align(ctx, CL_TILE_X, 1));
-- 
1.9.1