[Beignet] [PATCH] add conditions of pitch and h to enable userptr for climage_use_host_ptr
Guo Yejun
yejun.guo at intel.com
Fri Oct 16 23:07:32 PDT 2015
this regression issue is reported from conformance test, to enable
userptr for climage + use_host_ptr, the memory layout between the
host_ptr (for CPU) and drm bo (for GPU) must be the same. it means
bo's row pitch should be the same as image's row pitch, and h should
be the same as aligned h.
Signed-off-by: Guo Yejun <yejun.guo at intel.com>
---
src/cl_mem.c | 5 ++++-
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/src/cl_mem.c b/src/cl_mem.c
index 561e0a4..dd2040b 100644
--- a/src/cl_mem.c
+++ b/src/cl_mem.c
@@ -838,7 +838,8 @@ _cl_mem_new_image(cl_context ctx,
if (ctx->device->host_unified_memory && data != NULL && (flags & CL_MEM_USE_HOST_PTR)) {
int cacheline_size = 0;
cl_get_device_info(ctx->device, CL_DEVICE_GLOBAL_MEM_CACHELINE_SIZE, sizeof(cacheline_size), &cacheline_size, NULL);
- if (ALIGN((unsigned long)data, cacheline_size) == (unsigned long)data) { //might more conditions here
+ if (ALIGN((unsigned long)data, cacheline_size) == (unsigned long)data &&
+ ALIGN(h, cl_buffer_get_tiling_align(ctx, CL_NO_TILE, 1)) == h) {
tiling = CL_NO_TILE;
enableUserptr = 1;
}
@@ -847,6 +848,8 @@ _cl_mem_new_image(cl_context ctx,
/* Tiling requires to align both pitch and height */
if (tiling == CL_NO_TILE) {
aligned_pitch = w * bpp;
+ if (aligned_pitch < pitch && enableUserptr)
+ aligned_pitch = pitch;
if(image_type == CL_MEM_OBJECT_IMAGE1D_ARRAY || image_type == CL_MEM_OBJECT_IMAGE2D_ARRAY)
aligned_h = ALIGN(h, cl_buffer_get_tiling_align(ctx, CL_NO_TILE, 1));
else
--
1.9.1
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