[Beignet] [PATCH] fix a regression issue caused by LocalCopyPropagation

[Yang, Rong R]

Pushed.

> -----Original Message-----
> From: Guo, Yejun
> Sent: Monday, October 19, 2015 16:25
> To: Yang, Rong R; beignet at lists.freedesktop.org
> Subject: RE: [Beignet] [PATCH] fix a regression issue caused by
> LocalCopyPropagation
> 
> Good catch, from hw spec, and, not, or, xor 's srcmod is logical, I can send
> another patch to complete the list.
> 
> -----Original Message-----
> From: Yang, Rong R
> Sent: Monday, October 19, 2015 4:16 PM
> To: Guo, Yejun; beignet at lists.freedesktop.org
> Cc: Guo, Yejun
> Subject: RE: [Beignet] [PATCH] fix a regression issue caused by
> LocalCopyPropagation
> 
> Only and and' srcmod is logical? How about other logic instructions?
> 
> > -----Original Message-----
> > From: Beignet [mailto:beignet-bounces at lists.freedesktop.org] On Behalf
> > Of Guo Yejun
> > Sent: Tuesday, October 13, 2015 8:44
> > To: beignet at lists.freedesktop.org
> > Cc: Guo, Yejun
> > Subject: [Beignet] [PATCH] fix a regression issue caused by
> > LocalCopyPropagation
> >
> > on BDW+, for AND, SrcMod value indicates a logical source modifier.
> >
> > so, the below SELECTION IRs could not be optimized since abs is not a
> > logical source modifier
> >
> > MOV(16)             %2802<1>:D	:	(abs)%2801<8,8,1>:D
> > AND(16)             %2836<1>:D	:	%2802<8,8,1>:D	255:D
> >
> > Signed-off-by: Guo Yejun <yejun.guo at intel.com>
> > ---
> >  backend/src/backend/gen_insn_selection.cpp          | 4 ++++
> >  backend/src/backend/gen_insn_selection.hpp          | 6 ++++++
> >  backend/src/backend/gen_insn_selection_optimize.cpp | 4 ++++
> >  3 files changed, 14 insertions(+)
> >
> > diff --git a/backend/src/backend/gen_insn_selection.cpp
> > b/backend/src/backend/gen_insn_selection.cpp
> > index da437d1..9714e3e 100644
> > --- a/backend/src/backend/gen_insn_selection.cpp
> > +++ b/backend/src/backend/gen_insn_selection.cpp
> > @@ -2123,6 +2123,7 @@ namespace gbe
> >
> >    Selection75::Selection75(GenContext &ctx) : Selection(ctx) {
> >      this->opaque->setSlowByteGather(false);
> > +    opt_features = 0;
> >    }
> >
> >    Selection8::Selection8(GenContext &ctx) : Selection(ctx) { @@
> > -2130,6
> > +2131,7 @@ namespace gbe
> >      this->opaque->setHasLongType(true);
> >      this->opaque->setSlowByteGather(true);
> >      this->opaque->setHasHalfType(true);
> > +    opt_features = SIOF_OP_AND_LOGICAL_SRCMOD;
> >    }
> >
> >    SelectionChv::SelectionChv(GenContext &ctx) : Selection(ctx) { @@
> > -2138,6
> > +2140,7 @@ namespace gbe
> >      this->opaque->setLongRegRestrict(true);
> >      this->opaque->setSlowByteGather(true);
> >      this->opaque->setHasHalfType(true);
> > +    opt_features = SIOF_OP_AND_LOGICAL_SRCMOD;
> >    }
> >
> >    Selection9::Selection9(GenContext &ctx) : Selection(ctx) { @@
> > -2146,6
> > +2149,7 @@ namespace gbe
> >      this->opaque->setLdMsgOrder(LD_MSG_ORDER_SKL);
> >      this->opaque->setSlowByteGather(true);
> >      this->opaque->setHasHalfType(true);
> > +    opt_features = SIOF_OP_AND_LOGICAL_SRCMOD;
> >    }
> >
> >    void Selection::Opaque::TYPED_WRITE(GenRegister *msgs, uint32_t
> > msgNum, diff --git a/backend/src/backend/gen_insn_selection.hpp
> > b/backend/src/backend/gen_insn_selection.hpp
> > index 275eb9c..f313786 100644
> > --- a/backend/src/backend/gen_insn_selection.hpp
> > +++ b/backend/src/backend/gen_insn_selection.hpp
> > @@ -226,6 +226,12 @@ namespace gbe
> >      bool removeSimpleIfEndif;
> >    };
> >
> > +  enum SEL_IR_OPT_FEATURE {
> > +    //for OP_AND, on BDW+, SrcMod value indicates a logical source
> modifier
> > +    //            on PRE-BDW, SrcMod value indicates a numeric source modifier
> > +    SIOF_OP_AND_LOGICAL_SRCMOD = 1 << 0,  };
> > +
> >    /*! Owns the selection engine */
> >    class GenContext;
> >    /*! Selection engine produces the pre-ISA instruction blocks */
> > diff --git a/backend/src/backend/gen_insn_selection_optimize.cpp
> > b/backend/src/backend/gen_insn_selection_optimize.cpp
> > index 3f2ae2f..939dd18 100644
> > --- a/backend/src/backend/gen_insn_selection_optimize.cpp
> > +++ b/backend/src/backend/gen_insn_selection_optimize.cpp
> > @@ -170,6 +170,10 @@ namespace gbe
> >      if (insn.isWrite() || insn.isRead()) //register in selection vector
> >        return false;
> >
> > +    if (features & SIOF_OP_AND_LOGICAL_SRCMOD)
> > +      if (insn.opcode == SEL_OP_AND && (info->replacement.absolute ||
> > info->replacement.negation))
> > +        return false;
> > +
> >      if (info->replacementOverwritten)
> >        return false;
> >
> > --
> > 1.9.1
> >
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