[Beignet] [PATCH] GBE: Fix unaligned load/store issues.

[Ruiling Song]

1. need support float.
2. get correct element type.
3. should use ir::TYPE_U8 for byte store.

Signed-off-by: Ruiling Song <ruiling.song at intel.com>
---
 backend/src/llvm/llvm_gen_backend.cpp | 9 +++++----
 1 file changed, 5 insertions(+), 4 deletions(-)

diff --git a/backend/src/llvm/llvm_gen_backend.cpp b/backend/src/llvm/llvm_gen_backend.cpp
index 980996e..ad10890 100644
--- a/backend/src/llvm/llvm_gen_backend.cpp
+++ b/backend/src/llvm/llvm_gen_backend.cpp
@@ -4386,7 +4386,6 @@ namespace gbe
   void GenWriter::emitUnalignedDQLoadStore(ir::Register ptr, Value *llvmValues, ir::AddressSpace addrSpace, ir::Register bti, bool isLoad, bool dwAligned, bool fixedBTI)
   {
     Type *llvmType = llvmValues->getType();
-    const ir::Type type = getType(ctx, llvmType);
     unsigned byteSize = getTypeByteSize(unit, llvmType);
 
     Type *elemType = llvmType;
@@ -4396,6 +4395,7 @@ namespace gbe
       elemType = vectorType->getElementType();
       elemNum = vectorType->getNumElements();
     }
+    const ir::Type type = getType(ctx, elemType);
 
     vector<ir::Register> tupleData;
     for (uint32_t elemID = 0; elemID < elemNum; ++elemID) {
@@ -4438,7 +4438,7 @@ namespace gbe
           ctx.LOADI(ir::TYPE_S32, offset, immIndex);
           ctx.ADD(ir::TYPE_S32, addr, ptr, offset);
         }
-       ctx.STORE(type, addr, addrSpace, dwAligned, fixedBTI, bti, reg);
+       ctx.STORE(ir::TYPE_U8, addr, addrSpace, dwAligned, fixedBTI, bti, reg);
       }
     }
   }
@@ -4492,9 +4492,10 @@ namespace gbe
     else
       ptr = pointer;
 
+    unsigned primitiveBits = scalarType->getPrimitiveSizeInBits();
     if (!dwAligned
-       && (scalarType == IntegerType::get(I.getContext(), 64)
-          || scalarType == IntegerType::get(I.getContext(), 32))
+       && (primitiveBits == 64
+          || primitiveBits == 32)
        ) {
       emitUnalignedDQLoadStore(ptr, llvmValues, addrSpace, btiReg, isLoad, dwAligned, fixedBTI);
       return;
-- 
2.3.1