[Beignet] [PATCH 2/5] Backend: Delete LOAD_DF_IMM instruction.
junyan.he at inbox.com
junyan.he at inbox.com
Tue Oct 27 03:36:15 PDT 2015
From: Junyan He <junyan.he at linux.intel.com>
Double is supported on BDW later platforms, just normal MOV
can handle the loading of double. So no need for LOAD_DF_IMM
anymore.
Signed-off-by: Junyan He <junyan.he at linux.intel.com>
---
backend/src/backend/gen75_encoder.cpp | 30 ------------------------------
backend/src/backend/gen75_encoder.hpp | 1 -
backend/src/backend/gen8_encoder.cpp | 28 ----------------------------
backend/src/backend/gen8_encoder.hpp | 1 -
backend/src/backend/gen_context.cpp | 3 ---
backend/src/backend/gen_encoder.cpp | 29 -----------------------------
backend/src/backend/gen_encoder.hpp | 1 -
backend/src/backend/gen_insn_selection.cpp | 5 ++---
backend/src/backend/gen_insn_selection.hxx | 1 -
9 files changed, 2 insertions(+), 97 deletions(-)
diff --git a/backend/src/backend/gen75_encoder.cpp b/backend/src/backend/gen75_encoder.cpp
index 5d1a964..fc37991 100644
--- a/backend/src/backend/gen75_encoder.cpp
+++ b/backend/src/backend/gen75_encoder.cpp
@@ -221,36 +221,6 @@ namespace gbe
}
}
-
- void Gen75Encoder::LOAD_DF_IMM(GenRegister dest, GenRegister tmp, double value) {
- union { double d; unsigned u[2]; } u;
- u.d = value;
- GenRegister r = GenRegister::retype(tmp, GEN_TYPE_UD);
- push();
- curr.predicate = GEN_PREDICATE_NONE;
- curr.noMask = 1;
- curr.execWidth = 1;
- MOV(r, GenRegister::immud(u.u[0]));
- MOV(GenRegister::suboffset(r, 1), GenRegister::immud(u.u[1]));
- pop();
- r.type = GEN_TYPE_DF;
- r.vstride = GEN_VERTICAL_STRIDE_0;
- r.width = GEN_WIDTH_1;
- r.hstride = GEN_HORIZONTAL_STRIDE_0;
- push();
- uint32_t width = curr.execWidth;
- curr.execWidth = 8;
- curr.predicate = GEN_PREDICATE_NONE;
- curr.noMask = 1;
- curr.quarterControl = GEN_COMPRESSION_Q1;
- MOV(dest, r);
- if (width == 16) {
- curr.quarterControl = GEN_COMPRESSION_Q2;
- MOV(GenRegister::offset(dest, 2), r);
- }
- pop();
- }
-
void Gen75Encoder::JMPI(GenRegister src, bool longjmp) {
alu2(this, GEN_OPCODE_JMPI, GenRegister::ip(), GenRegister::ip(), src);
}
diff --git a/backend/src/backend/gen75_encoder.hpp b/backend/src/backend/gen75_encoder.hpp
index f5044c0..d06f393 100644
--- a/backend/src/backend/gen75_encoder.hpp
+++ b/backend/src/backend/gen75_encoder.hpp
@@ -42,7 +42,6 @@ namespace gbe
virtual void JMPI(GenRegister src, bool longjmp = false);
/*! Patch JMPI/BRC/BRD (located at index insnID) with the given jump distance */
virtual void patchJMPI(uint32_t insnID, int32_t jip, int32_t uip);
- virtual void LOAD_DF_IMM(GenRegister dest, GenRegister tmp, double value);
virtual void ATOMIC(GenRegister dst, uint32_t function, GenRegister src, GenRegister bti, uint32_t srcNum);
virtual void UNTYPED_READ(GenRegister dst, GenRegister src, GenRegister bti, uint32_t elemNum);
virtual void UNTYPED_WRITE(GenRegister src, GenRegister bti, uint32_t elemNum);
diff --git a/backend/src/backend/gen8_encoder.cpp b/backend/src/backend/gen8_encoder.cpp
index 98c3917..16b3fc6 100644
--- a/backend/src/backend/gen8_encoder.cpp
+++ b/backend/src/backend/gen8_encoder.cpp
@@ -227,34 +227,6 @@ namespace gbe
this->setSrc1(insn, bti);
}
}
- void Gen8Encoder::LOAD_DF_IMM(GenRegister dest, GenRegister tmp, double value) {
- union { double d; unsigned u[2]; } u;
- u.d = value;
- GenRegister r = GenRegister::retype(tmp, GEN_TYPE_UD);
- push();
- curr.predicate = GEN_PREDICATE_NONE;
- curr.noMask = 1;
- curr.execWidth = 1;
- MOV(r, GenRegister::immud(u.u[0]));
- MOV(GenRegister::suboffset(r, 1), GenRegister::immud(u.u[1]));
- pop();
- r.type = GEN_TYPE_DF;
- r.vstride = GEN_VERTICAL_STRIDE_0;
- r.width = GEN_WIDTH_1;
- r.hstride = GEN_HORIZONTAL_STRIDE_0;
- push();
- uint32_t width = curr.execWidth;
- curr.execWidth = 8;
- curr.predicate = GEN_PREDICATE_NONE;
- curr.noMask = 1;
- curr.quarterControl = GEN_COMPRESSION_Q1;
- MOV(dest, r);
- if (width == 16) {
- curr.quarterControl = GEN_COMPRESSION_Q2;
- MOV(GenRegister::offset(dest, 2), r);
- }
- pop();
- }
void Gen8Encoder::LOAD_INT64_IMM(GenRegister dest, GenRegister value) {
MOV(dest, value);
diff --git a/backend/src/backend/gen8_encoder.hpp b/backend/src/backend/gen8_encoder.hpp
index 2aa074f..8c447ea 100644
--- a/backend/src/backend/gen8_encoder.hpp
+++ b/backend/src/backend/gen8_encoder.hpp
@@ -42,7 +42,6 @@ namespace gbe
virtual void patchJMPI(uint32_t insnID, int32_t jip, int32_t uip);
virtual void F16TO32(GenRegister dest, GenRegister src0);
virtual void F32TO16(GenRegister dest, GenRegister src0);
- virtual void LOAD_DF_IMM(GenRegister dest, GenRegister tmp, double value);
virtual void LOAD_INT64_IMM(GenRegister dest, GenRegister value);
virtual void ATOMIC(GenRegister dst, uint32_t function, GenRegister src, GenRegister bti, uint32_t srcNum);
virtual void UNTYPED_READ(GenRegister dst, GenRegister src, GenRegister bti, uint32_t elemNum);
diff --git a/backend/src/backend/gen_context.cpp b/backend/src/backend/gen_context.cpp
index cad7802..2fd295d 100644
--- a/backend/src/backend/gen_context.cpp
+++ b/backend/src/backend/gen_context.cpp
@@ -329,9 +329,6 @@ namespace gbe
GenRegister src = ra->genReg(insn.src(0));
GenRegister tmp = ra->genReg(insn.dst(1));
switch (insn.opcode) {
- case SEL_OP_LOAD_DF_IMM:
- p->LOAD_DF_IMM(dst, tmp, src.value.df);
- break;
case SEL_OP_CONVI_TO_I64: {
GenRegister middle = src;
if(src.type == GEN_TYPE_B || src.type == GEN_TYPE_W) {
diff --git a/backend/src/backend/gen_encoder.cpp b/backend/src/backend/gen_encoder.cpp
index a6daa0d..4adef70 100644
--- a/backend/src/backend/gen_encoder.cpp
+++ b/backend/src/backend/gen_encoder.cpp
@@ -728,35 +728,6 @@ namespace gbe
this->alu3(GEN_OPCODE_##OP, dest, src0, src1, src2); \
}
- void GenEncoder::LOAD_DF_IMM(GenRegister dest, GenRegister tmp, double value) {
- union { double d; unsigned u[2]; } u;
- u.d = value;
- GenRegister r = GenRegister::retype(tmp, GEN_TYPE_UD);
- push();
- curr.predicate = GEN_PREDICATE_NONE;
- curr.noMask = 1;
- curr.execWidth = 1;
- MOV(r, GenRegister::immud(u.u[1]));
- MOV(GenRegister::suboffset(r, 1), GenRegister::immud(u.u[0]));
- pop();
- r.type = GEN_TYPE_DF;
- r.vstride = GEN_VERTICAL_STRIDE_0;
- r.width = GEN_WIDTH_1;
- r.hstride = GEN_HORIZONTAL_STRIDE_0;
- push();
- uint32_t width = curr.execWidth;
- curr.execWidth = 8;
- curr.predicate = GEN_PREDICATE_NONE;
- curr.noMask = 1;
- curr.quarterControl = GEN_COMPRESSION_Q1;
- MOV(dest, r);
- if (width == 16) {
- curr.quarterControl = GEN_COMPRESSION_Q2;
- MOV(GenRegister::offset(dest, 2), r);
- }
- pop();
- }
-
void GenEncoder::LOAD_INT64_IMM(GenRegister dest, GenRegister value) {
GenRegister u0 = GenRegister::immd((int)value.value.i64), u1 = GenRegister::immd(value.value.i64 >> 32);
MOV(dest.bottom_half(), u0);
diff --git a/backend/src/backend/gen_encoder.hpp b/backend/src/backend/gen_encoder.hpp
index 3e9866c..c6e9e4f 100644
--- a/backend/src/backend/gen_encoder.hpp
+++ b/backend/src/backend/gen_encoder.hpp
@@ -134,7 +134,6 @@ namespace gbe
virtual void F16TO32(GenRegister dest, GenRegister src0);
virtual void F32TO16(GenRegister dest, GenRegister src0);
- virtual void LOAD_DF_IMM(GenRegister dest, GenRegister tmp, double value);
virtual void LOAD_INT64_IMM(GenRegister dest, GenRegister value);
/*! Barrier message (to synchronize threads of a workgroup) */
void BARRIER(GenRegister src);
diff --git a/backend/src/backend/gen_insn_selection.cpp b/backend/src/backend/gen_insn_selection.cpp
index 869f13b..b027ca8 100644
--- a/backend/src/backend/gen_insn_selection.cpp
+++ b/backend/src/backend/gen_insn_selection.cpp
@@ -516,7 +516,6 @@ namespace gbe
INLINE void OP(Reg dst, Reg src0, Reg src1, GenRegister tmp[6]) { I64Shift(SEL_OP_##OP, dst, src0, src1, tmp); }
ALU1(MOV)
ALU1(READ_ARF)
- ALU1WithTemp(LOAD_DF_IMM)
ALU1(LOAD_INT64_IMM)
ALU1(RNDZ)
ALU1(RNDE)
@@ -3347,12 +3346,12 @@ namespace gbe
ir::half hf = imm.getHalfValue();
sel.MOV(GenRegister::retype(dst, GEN_TYPE_HF), GenRegister::immh(hf.getVal()));
break;
- }
+ }
case TYPE_U16: sel.MOV(dst, GenRegister::immuw(imm.getIntegerValue())); break;
case TYPE_S16: sel.MOV(dst, GenRegister::immw(imm.getIntegerValue())); break;
case TYPE_U8: sel.MOV(dst, GenRegister::immuw(imm.getIntegerValue())); break;
case TYPE_S8: sel.MOV(dst, GenRegister::immw(imm.getIntegerValue())); break;
- case TYPE_DOUBLE: sel.LOAD_DF_IMM(dst, GenRegister::immdf(imm.getDoubleValue()), sel.selReg(sel.reg(FAMILY_QWORD), TYPE_U64)); break;
+ case TYPE_DOUBLE: sel.MOV(dst, GenRegister::immdf(imm.getDoubleValue())); break;
case TYPE_S64: sel.LOAD_INT64_IMM(dst, GenRegister::immint64(imm.getIntegerValue())); break;
case TYPE_U64: sel.LOAD_INT64_IMM(dst, GenRegister::immuint64(imm.getIntegerValue())); break;
default: NOT_SUPPORTED;
diff --git a/backend/src/backend/gen_insn_selection.hxx b/backend/src/backend/gen_insn_selection.hxx
index 1f248be..fa3cb2e 100644
--- a/backend/src/backend/gen_insn_selection.hxx
+++ b/backend/src/backend/gen_insn_selection.hxx
@@ -1,7 +1,6 @@
DECL_SELECTION_IR(LABEL, LabelInstruction)
DECL_SELECTION_IR(MOV, UnaryInstruction)
DECL_SELECTION_IR(BSWAP, UnaryWithTempInstruction)
-DECL_SELECTION_IR(LOAD_DF_IMM, UnaryWithTempInstruction)
DECL_SELECTION_IR(LOAD_INT64_IMM, UnaryInstruction)
DECL_SELECTION_IR(NOT, UnaryInstruction)
DECL_SELECTION_IR(LZD, UnaryInstruction)
--
1.9.1
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