[Beignet] [PATCH 2/7] transfer debugloc from llvm ir to gen ir
Bai Yannan
yannan.bai at intel.com
Fri Sep 18 02:01:52 PDT 2015
Signed-off-by: Bai Yannan <yannan.bai at intel.com>
---
backend/src/ir/instruction.cpp | 13 ++++
backend/src/ir/instruction.hpp | 11 ++-
backend/src/llvm/llvm_gen_backend.cpp | 136 +++++++++++++++++++++++++++++++---
3 files changed, 150 insertions(+), 10 deletions(-)
diff --git a/backend/src/ir/instruction.cpp b/backend/src/ir/instruction.cpp
index f93c528..a7e7396 100644
--- a/backend/src/ir/instruction.cpp
+++ b/backend/src/ir/instruction.cpp
@@ -1648,6 +1648,19 @@ END_FUNCTION(Instruction, Register)
opcode == OP_ATOMIC;
}
+ void Instruction::setDBGInfo(unsigned int line, unsigned int col) {
+ if(line == 0) return;
+ DBGInfo.hasDBGInfo = true;
+ DBGInfo.line = line;
+ DBGInfo.col = col;
+ }
+
+ void Instruction::initDBGInfo() {
+ DBGInfo.line = 0;
+ DBGInfo.col = 0;
+ DBGInfo.hasDBGInfo = false;
+ }
+
#define DECL_MEM_FN(CLASS, RET, PROTOTYPE, CALL) \
RET CLASS::PROTOTYPE const { \
return reinterpret_cast<const internal::CLASS*>(this)->CALL; \
diff --git a/backend/src/ir/instruction.hpp b/backend/src/ir/instruction.hpp
index cf8d839..facae1d 100644
--- a/backend/src/ir/instruction.hpp
+++ b/backend/src/ir/instruction.hpp
@@ -139,16 +139,18 @@ namespace ir {
INLINE Instruction(const Instruction &other) :
InstructionBase(reinterpret_cast<const char*>(&other.opcode)) {
parent = other.parent;
+ initDBGInfo();
}
private:
/*! To be consistant with copy constructor */
INLINE Instruction &operator= (const Instruction &other) { return *this; }
+ void initDBGInfo();
public:
/*! Nothing to do here */
INLINE ~Instruction(void) {}
/*! Uninitialized instruction */
- INLINE Instruction(void) {}
+ INLINE Instruction(void) { initDBGInfo(); }
/*! Get the number of sources for this instruction */
uint32_t getSrcNum(void) const;
/*! Get the number of destination for this instruction */
@@ -185,6 +187,7 @@ namespace ir {
void remove(void);
/* Insert the instruction after the previous one. */
void insert(Instruction *prev, Instruction ** new_ins = NULL);
+ void setDBGInfo(unsigned int line, unsigned int col);
/*! Indicates if the instruction belongs to instruction type T. Typically, T
* can be BinaryInstruction, UnaryInstruction, LoadInstruction and so on
*/
@@ -194,8 +197,14 @@ namespace ir {
/*! max_src for store instruction (vec16 + addr) */
static const uint32_t MAX_SRC_NUM = 32;
static const uint32_t MAX_DST_NUM = 32;
+ struct {
+ unsigned int line; // the line of cl source which interprets to this instruction
+ unsigned int col;
+ bool hasDBGInfo;
+ }DBGInfo;// save debug infomation for each instruction
protected:
BasicBlock *parent; //!< The basic block containing the instruction
+
GBE_CLASS(Instruction); //!< Use internal allocators
};
diff --git a/backend/src/llvm/llvm_gen_backend.cpp b/backend/src/llvm/llvm_gen_backend.cpp
index 238370a..1ce5e19 100644
--- a/backend/src/llvm/llvm_gen_backend.cpp
+++ b/backend/src/llvm/llvm_gen_backend.cpp
@@ -193,6 +193,19 @@ using namespace llvm;
}
// end define SETDEBUGLOCATION
+#define GET_INSN_DBGLOC1(I) dg = I.getDebugLoc()
+#define GET_INSN_DBGLOC2(I) dg = I->getDebugLoc()
+#define GET_INSN_DBGLOC3(I) \
+ llvm::Instruction * It = dyn_cast<llvm::Instruction>(I); \
+ dg = It->getDebugLoc()
+#define SET_GENIR_DBGINFO(I, FLAG) \
+if(OCL_PROFILING){ \
+ llvm::DebugLoc dg; \
+ GET_INSN_DBGLOC##FLAG(I); \
+ gbe::ir::BasicBlock * bb = ctx.getBlock(); \
+ gbe::ir::Instruction *curI = bb->getLastInstruction(); \
+ curI->setDBGInfo(dg.getLine(), dg.getCol());}
+// end define SET_GENIR_DBGINFO
namespace gbe
{
@@ -1853,9 +1866,11 @@ namespace gbe
isa<UndefValue>(extractConstantElem(CPV, 0)))
continue;
ctx.MOV(type, dst, getRegister(CP));
+ SET_GENIR_DBGINFO(PN,2);
} else if (regTranslator.valueExists(IV,0) || dyn_cast<Constant>(IV)) {
const ir::Register src = this->getRegister(IV);
ctx.MOV(type, dst, src);
+ SET_GENIR_DBGINFO(PN,2);
}
assert(!ctx.getBlock()->undefPhiRegs.contains(dst));
ctx.getBlock()->definedPhiRegs.insert(dst);
@@ -2791,8 +2806,10 @@ namespace gbe
const ir::Register src = this->getRegister(I.getOperand(0));
const ir::RegisterFamily family = fn.getRegisterFamily(dst);
ctx.MOV(ir::getType(family), dst, src);
+ SET_GENIR_DBGINFO(I,1);
}
ctx.RET();
+ //SET_GENIR_DBGINFO(I, 1);
}
void GenWriter::regAllocateBinaryOperator(Instruction &I) {
@@ -2820,6 +2837,7 @@ namespace gbe
const ir::Register dst = this->getRegister(&I);
const ir::Register src0 = this->getRegister(I.getOperand(0));
const ir::Register src1 = this->getRegister(I.getOperand(1));
+ bool isSupported = true;
switch (I.getOpcode()) {
case Instruction::Add:
@@ -2840,8 +2858,10 @@ namespace gbe
case Instruction::Shl: ctx.SHL(type, dst, src0, src1); break;
case Instruction::LShr: ctx.SHR(getUnsignedType(ctx, I.getType()), dst, src0, src1); break;
case Instruction::AShr: ctx.ASR(type, dst, src0, src1); break;
- default: NOT_SUPPORTED;
+ default: isSupported = false; NOT_SUPPORTED;
}
+ if(isSupported)
+ SET_GENIR_DBGINFO(I,1);
}
void GenWriter::regAllocateICmpInst(ICmpInst &I) {
@@ -2877,6 +2897,7 @@ namespace gbe
const ir::Register src1 = this->getRegister(I.getOperand(1));
// We must invert the condition to simplify the branch code
+ bool isSupported = true;
if (conditionSet.find(&I) != conditionSet.end()) {
switch (I.getPredicate()) {
case ICmpInst::ICMP_EQ: ctx.NE(type, dst, src0, src1); break;
@@ -2889,7 +2910,7 @@ namespace gbe
case ICmpInst::ICMP_SLT: ctx.GE(signedType, dst, src0, src1); break;
case ICmpInst::ICMP_UGT: ctx.LE(unsignedType, dst, src0, src1); break;
case ICmpInst::ICMP_SGT: ctx.LE(signedType, dst, src0, src1); break;
- default: NOT_SUPPORTED;
+ default: isSupported = false; NOT_SUPPORTED;
}
}
// Nothing special to do
@@ -2905,9 +2926,11 @@ namespace gbe
case ICmpInst::ICMP_SLT: ctx.LT(signedType, dst, src0, src1); break;
case ICmpInst::ICMP_UGT: ctx.GT(unsignedType, dst, src0, src1); break;
case ICmpInst::ICMP_SGT: ctx.GT(signedType, dst, src0, src1); break;
- default: NOT_SUPPORTED;
+ default: isSupported = false;NOT_SUPPORTED;
}
}
+ if(isSupported)
+ SET_GENIR_DBGINFO(I,1);
}
void GenWriter::regAllocateFCmpInst(FCmpInst &I) {
@@ -2927,6 +2950,7 @@ namespace gbe
const ir::Register src1 = this->getRegister(I.getOperand(1));
const ir::Register tmp = ctx.reg(getFamily(ctx, I.getType()));
Value *cv = ConstantInt::get(I.getType(), 1);
+ bool isSupported = true;
switch (I.getPredicate()) {
case ICmpInst::FCMP_OEQ: ctx.EQ(type, dst, src0, src1); break;
@@ -2953,38 +2977,47 @@ namespace gbe
ctx.NE(type, dst, src0, src0);
else {
ctx.ORD(type, tmp, src0, src1);
+ SET_GENIR_DBGINFO(I,1);
ctx.XOR(insnType, dst, tmp, getRegister(cv)); //TODO: Use NOT directly
}
break;
case ICmpInst::FCMP_UEQ:
ctx.NE(type, tmp, src0, src1);
+ SET_GENIR_DBGINFO(I,1);
ctx.XOR(insnType, dst, tmp, getRegister(cv));
break;
case ICmpInst::FCMP_UGT:
ctx.LE(type, tmp, src0, src1);
+ SET_GENIR_DBGINFO(I,1);
ctx.XOR(insnType, dst, tmp, getRegister(cv));
break;
case ICmpInst::FCMP_UGE:
ctx.LT(type, tmp, src0, src1);
+ SET_GENIR_DBGINFO(I,1);
ctx.XOR(insnType, dst, tmp, getRegister(cv));
break;
case ICmpInst::FCMP_ULT:
ctx.GE(type, tmp, src0, src1);
+ SET_GENIR_DBGINFO(I,1);
ctx.XOR(insnType, dst, tmp, getRegister(cv));
break;
case ICmpInst::FCMP_ULE:
ctx.GT(type, tmp, src0, src1);
+ SET_GENIR_DBGINFO(I,1);
ctx.XOR(insnType, dst, tmp, getRegister(cv));
break;
case ICmpInst::FCMP_UNE:
ctx.EQ(type, tmp, src0, src1);
+ SET_GENIR_DBGINFO(I,1);
ctx.XOR(insnType, dst, tmp, getRegister(cv));
break;
case ICmpInst::FCMP_TRUE:
ctx.MOV(insnType, dst, getRegister(cv));
break;
- default: NOT_SUPPORTED;
+ default: isSupported = false; NOT_SUPPORTED;
}
+ if(isSupported)
+ SET_GENIR_DBGINFO(I,1);
}
void GenWriter::regAllocateCastInst(CastInst &I) {
@@ -3053,6 +3086,7 @@ namespace gbe
const ir::Register dst = this->getRegister(&I);
const ir::Register src = this->getRegister(srcValue);
ctx.CVT(getType(ctx, dstType), getType(ctx, srcType), dst, src);
+ SET_GENIR_DBGINFO(I,1);
}
}
break;
@@ -3088,6 +3122,7 @@ namespace gbe
const ir::Tuple dstTuple = ctx.arrayTuple(&dstTupleData[0], dstElemNum);
ctx.BITCAST(dstType, srcType, dstTuple, srcTuple, dstElemNum, srcElemNum);
+ SET_GENIR_DBGINFO(I,1);
}
}
break; // nothing to emit here
@@ -3129,7 +3164,9 @@ namespace gbe
const ir::Register zeroReg = ctx.reg(family);
const ir::Register oneReg = ctx.reg(family);
ctx.LOADI(dstType, zeroReg, zero);
+ SET_GENIR_DBGINFO(I,1);
ctx.LOADI(dstType, oneReg, one);
+ SET_GENIR_DBGINFO(I,1);
const ir::Register dst = this->getRegister(&I);
const ir::Register src = this->getRegister(I.getOperand(0));
ctx.SEL(dstType, dst, src, oneReg, zeroReg);
@@ -3146,6 +3183,7 @@ namespace gbe
const ir::Register src = this->getRegister(I.getOperand(0));
ctx.CVT(dstType, srcType, dst, src);
}
+ SET_GENIR_DBGINFO(I,1);
}
break;
default: NOT_SUPPORTED;
@@ -3212,6 +3250,7 @@ namespace gbe
const ir::Register src0 = this->getRegister(I.getOperand(1));
const ir::Register src1 = this->getRegister(I.getOperand(2));
ctx.SEL(type, dst, cond, src0, src1);
+ SET_GENIR_DBGINFO(I,1);
}
void GenWriter::regAllocatePHINode(PHINode &I) {
@@ -3229,6 +3268,7 @@ namespace gbe
const ir::Register dst = this->getRegister(&I);
const ir::Register src = this->getRegister(copy);
ctx.MOV(type, dst, src);
+ SET_GENIR_DBGINFO(I,1);
phiMap.insert(std::make_pair(dst, src));
}
@@ -3249,6 +3289,7 @@ namespace gbe
GBE_ASSERT(labelMap.find(target) != labelMap.end());
const ir::LabelIndex labelIndex = labelMap[target];
ctx.BRA(labelIndex);
+ SET_GENIR_DBGINFO(I,1);
}
}
// The LLVM branch has two targets
@@ -3266,6 +3307,7 @@ namespace gbe
const ir::LabelIndex index = labelMap[taken];
const ir::Register reg = this->getRegister(condition);
ctx.BRA(index, reg);
+ SET_GENIR_DBGINFO(I,1);
// If non-taken target is the next block, there is nothing to do
BasicBlock *bb = I.getParent();
@@ -3277,7 +3319,9 @@ namespace gbe
GBE_ASSERT(labelMap.find(nonTaken) != labelMap.end());
const ir::LabelIndex untakenIndex = ctx.label();
ctx.LABEL(untakenIndex);
+ SET_GENIR_DBGINFO(I,1);
ctx.BRA(labelMap[nonTaken]);
+ SET_GENIR_DBGINFO(I,1);
}
}
@@ -3539,6 +3583,7 @@ namespace gbe
const ir::Register src = this->getRegister(*AI);
const ir::Register dst = this->getRegister(&I);
ctx.ALU1(opcode, type, dst, src);
+ SET_GENIR_DBGINFO(I,1);
}
void GenWriter::emitAtomicInst(CallInst &I, CallSite &CS, ir::AtomicOps opcode) {
@@ -3563,6 +3608,7 @@ namespace gbe
ir::ImmediateIndex immIndex = ctx.newImmediate((uint32_t)index);
btiReg = ctx.reg(ir::FAMILY_DWORD);
ctx.LOADI(ir::TYPE_U32, btiReg, immIndex);
+ SET_GENIR_DBGINFO(I,1);
} else {
addrSpace = ir::MEM_MIXED;
btiReg = this->getRegister(bti);
@@ -3571,6 +3617,7 @@ namespace gbe
const ir::RegisterFamily pointerFamily = ctx.getPointerFamily();
const ir::Register ptr = ctx.reg(pointerFamily);
ctx.SUB(ir::TYPE_U32, ptr, pointer, baseReg);
+ SET_GENIR_DBGINFO(I,1);
const ir::Register dst = this->getRegister(&I);
@@ -3586,6 +3633,7 @@ namespace gbe
}
const ir::Tuple srcTuple = ctx.arrayTuple(&src[0], srcNum);
ctx.ATOMIC(opcode, dst, addrSpace, btiReg, fixedBTI, srcTuple);
+ SET_GENIR_DBGINFO(I,1);
}
/* append a new sampler. should be called before any reference to
@@ -3631,6 +3679,7 @@ namespace gbe
const ir::Register src = ir::ocl::stackptr;
const ir::RegisterFamily family = fn.getRegisterFamily(dst);
ctx.MOV(ir::getType(family), dst, src);
+ SET_GENIR_DBGINFO(I,1);
}
break;
case Intrinsic::stackrestore:
@@ -3639,6 +3688,7 @@ namespace gbe
const ir::Register src = this->getRegister(I.getOperand(0));
const ir::RegisterFamily family = fn.getRegisterFamily(dst);
ctx.MOV(ir::getType(family), dst, src);
+ SET_GENIR_DBGINFO(I,1);
}
break;
#if LLVM_VERSION_MINOR >= 2
@@ -3650,7 +3700,9 @@ namespace gbe
const ir::Register src1 = this->getRegister(I.getOperand(1));
const ir::Register src2 = this->getRegister(I.getOperand(2));
ctx.MUL(ir::TYPE_FLOAT, tmp, src0, src1);
+ SET_GENIR_DBGINFO(I,1);
ctx.ADD(ir::TYPE_FLOAT, dst, tmp, src2);
+ SET_GENIR_DBGINFO(I,1);
}
break;
case Intrinsic::lifetime_start:
@@ -3670,10 +3722,12 @@ namespace gbe
const ir::Register src0 = this->getRegister(I.getOperand(0));
const ir::Register src1 = this->getRegister(I.getOperand(1));
ctx.ADD(dst0Type, dst0, src0, src1);
+ SET_GENIR_DBGINFO(I,1);
ir::Register overflow = this->getRegister(&I, 1);
const ir::Type unsignedType = makeTypeUnsigned(dst0Type);
ctx.LT(unsignedType, overflow, dst0, src1);
+ SET_GENIR_DBGINFO(I,1);
}
break;
case Intrinsic::usub_with_overflow:
@@ -3685,10 +3739,12 @@ namespace gbe
const ir::Register src0 = this->getRegister(I.getOperand(0));
const ir::Register src1 = this->getRegister(I.getOperand(1));
ctx.SUB(dst0Type, dst0, src0, src1);
+ SET_GENIR_DBGINFO(I,1);
ir::Register overflow = this->getRegister(&I, 1);
const ir::Type unsignedType = makeTypeUnsigned(dst0Type);
ctx.GT(unsignedType, overflow, dst0, src0);
+ SET_GENIR_DBGINFO(I,1);
}
break;
case Intrinsic::sadd_with_overflow:
@@ -3723,18 +3779,24 @@ namespace gbe
const ir::RegisterFamily family = getFamily(tmpType);
const ir::Register immReg = ctx.reg(family);
ctx.LOADI(ir::TYPE_S32, immReg, imm);
+ SET_GENIR_DBGINFO(I,1);
ir::Register tmp0 = ctx.reg(getFamily(tmpType));
ir::Register tmp1 = ctx.reg(getFamily(tmpType));
ir::Register tmp2 = ctx.reg(getFamily(tmpType));
ctx.CVT(tmpType, srcType, tmp0, src);
+ SET_GENIR_DBGINFO(I,1);
ctx.ALU1(ir::OP_LZD, tmpType, tmp1, tmp0);
+ SET_GENIR_DBGINFO(I,1);
ctx.SUB(tmpType, tmp2, tmp1, immReg);
+ SET_GENIR_DBGINFO(I,1);
ctx.CVT(dstType, tmpType, dst, tmp2);
+ SET_GENIR_DBGINFO(I,1);
}
else
{
ctx.ALU1(ir::OP_LZD, dstType, dst, src);
+ SET_GENIR_DBGINFO(I,1);
}
}
break;
@@ -3746,6 +3808,7 @@ namespace gbe
const ir::Register src1 = this->getRegister(I.getOperand(1));
const ir::Register src2 = this->getRegister(I.getOperand(2));
ctx.MAD(srcType, dst, src0, src1, src2);
+ SET_GENIR_DBGINFO(I,1);
}
break;
case Intrinsic::sqrt: this->emitUnaryCallInst(I,CS,ir::OP_SQR); break;
@@ -3766,6 +3829,7 @@ namespace gbe
const ir::Register src1 = this->getRegister(*AI);
const ir::Register dst = this->getRegister(&I);
ctx.POW(ir::TYPE_FLOAT, dst, src0, src1);
+ SET_GENIR_DBGINFO(I,1);
break;
}
default: NOT_IMPLEMENTED;
@@ -3792,6 +3856,7 @@ namespace gbe
const ir::Register src = this->getRegister(*AI);
const ir::Register dst = this->getRegister(&I);
ctx.ALU1(ir::OP_ABS, getType(ctx, (*AI)->getType()), dst, src);
+ SET_GENIR_DBGINFO(I,1);
break;
}
case GEN_OCL_SIMD_ALL:
@@ -3799,6 +3864,7 @@ namespace gbe
const ir::Register src = this->getRegister(*AI);
const ir::Register dst = this->getRegister(&I);
ctx.ALU1(ir::OP_SIMD_ALL, ir::TYPE_S32, dst, src);
+ SET_GENIR_DBGINFO(I,1);
break;
}
case GEN_OCL_SIMD_ANY:
@@ -3806,12 +3872,14 @@ namespace gbe
const ir::Register src = this->getRegister(*AI);
const ir::Register dst = this->getRegister(&I);
ctx.ALU1(ir::OP_SIMD_ANY, ir::TYPE_S32, dst, src);
+ SET_GENIR_DBGINFO(I,1);
break;
}
case GEN_OCL_READ_TM:
{
const ir::Register dst = this->getRegister(&I);
ctx.READ_ARF(ir::TYPE_U32, dst, ir::ARF_TM);
+ SET_GENIR_DBGINFO(I,1);
break;
}
case GEN_OCL_REGION:
@@ -3826,15 +3894,16 @@ namespace gbe
const ir::Register src = this->getRegister(*AI);
ctx.REGION(dst, src, x.getIntegerValue());
+ SET_GENIR_DBGINFO(I,1);
break;
}
case GEN_OCL_RSQ: this->emitUnaryCallInst(I,CS,ir::OP_RSQ); break;
case GEN_OCL_RCP: this->emitUnaryCallInst(I,CS,ir::OP_RCP); break;
case GEN_OCL_FORCE_SIMD8: ctx.setSimdWidth(8); break;
case GEN_OCL_FORCE_SIMD16: ctx.setSimdWidth(16); break;
- case GEN_OCL_LBARRIER: ctx.SYNC(ir::syncLocalBarrier); break;
- case GEN_OCL_GBARRIER: ctx.SYNC(ir::syncGlobalBarrier); break;
- case GEN_OCL_LGBARRIER: ctx.SYNC(ir::syncLocalBarrier | ir::syncGlobalBarrier); break;
+ case GEN_OCL_LBARRIER: ctx.SYNC(ir::syncLocalBarrier); SET_GENIR_DBGINFO(I,1);break;
+ case GEN_OCL_GBARRIER: ctx.SYNC(ir::syncGlobalBarrier); SET_GENIR_DBGINFO(I,1);break;
+ case GEN_OCL_LGBARRIER: ctx.SYNC(ir::syncLocalBarrier | ir::syncGlobalBarrier); SET_GENIR_DBGINFO(I,1);break;
case GEN_OCL_ATOMIC_ADD0:
case GEN_OCL_ATOMIC_ADD1: this->emitAtomicInst(I,CS,ir::ATOMIC_OP_ADD); break;
case GEN_OCL_ATOMIC_SUB0:
@@ -3874,6 +3943,7 @@ namespace gbe
ir::ImageInfoKey key(imageID, infoType);
const ir::Register infoReg = ctx.getFunction().getImageSet()->appendInfo(key, &ctx);
ctx.GET_IMAGE_INFO(infoType, reg, imageID, infoReg);
+ SET_GENIR_DBGINFO(I,1);
break;
}
@@ -3926,6 +3996,7 @@ namespace gbe
ctx.SAMPLE(imageID, dstTuple, srcTuple, imageDim, dstType == ir::TYPE_FLOAT,
requiredFloatCoord, sampler, samplerOffset);
+ SET_GENIR_DBGINFO(I,1);
break;
}
@@ -3957,6 +4028,7 @@ namespace gbe
}
const ir::Tuple srcTuple = ctx.arrayTuple(&srcTupleData[0], imageDim + 4);
ctx.TYPED_WRITE(imageID, srcTuple, imageDim + 4, srcType, ir::TYPE_U32);
+ SET_GENIR_DBGINFO(I,1);
break;
}
case GEN_OCL_MUL_HI_INT:
@@ -3965,6 +4037,7 @@ namespace gbe
GBE_ASSERT(AI != AE); const ir::Register src1 = this->getRegister(*AI); ++AI;
const ir::Register dst = this->getRegister(&I);
ctx.MUL_HI(getType(ctx, I.getType()), dst, src0, src1);
+ SET_GENIR_DBGINFO(I,1);
break;
}
case GEN_OCL_MUL_HI_UINT:
@@ -3973,6 +4046,7 @@ namespace gbe
GBE_ASSERT(AI != AE); const ir::Register src1 = this->getRegister(*AI); ++AI;
const ir::Register dst = this->getRegister(&I);
ctx.MUL_HI(getUnsignedType(ctx, I.getType()), dst, src0, src1);
+ SET_GENIR_DBGINFO(I,1);
break;
}
case GEN_OCL_MUL_HI_I64:
@@ -3981,6 +4055,7 @@ namespace gbe
GBE_ASSERT(AI != AE); const ir::Register src1 = this->getRegister(*AI); ++AI;
const ir::Register dst = this->getRegister(&I);
ctx.I64_MUL_HI(getType(ctx, I.getType()), dst, src0, src1);
+ SET_GENIR_DBGINFO(I,1);
break;
}
case GEN_OCL_MUL_HI_UI64:
@@ -3989,6 +4064,7 @@ namespace gbe
GBE_ASSERT(AI != AE); const ir::Register src1 = this->getRegister(*AI); ++AI;
const ir::Register dst = this->getRegister(&I);
ctx.I64_MUL_HI(getUnsignedType(ctx, I.getType()), dst, src0, src1);
+ SET_GENIR_DBGINFO(I,1);
break;
}
case GEN_OCL_UPSAMPLE_SHORT:
@@ -3997,6 +4073,7 @@ namespace gbe
GBE_ASSERT(AI != AE); const ir::Register src1 = this->getRegister(*AI); ++AI;
const ir::Register dst = this->getRegister(&I);
ctx.UPSAMPLE_SHORT(getType(ctx, I.getType()), dst, src0, src1);
+ SET_GENIR_DBGINFO(I,1);
break;
}
case GEN_OCL_UPSAMPLE_INT:
@@ -4005,6 +4082,7 @@ namespace gbe
GBE_ASSERT(AI != AE); const ir::Register src1 = this->getRegister(*AI); ++AI;
const ir::Register dst = this->getRegister(&I);
ctx.UPSAMPLE_INT(getType(ctx, I.getType()), dst, src0, src1);
+ SET_GENIR_DBGINFO(I,1);
break;
}
case GEN_OCL_UPSAMPLE_LONG:
@@ -4013,6 +4091,7 @@ namespace gbe
GBE_ASSERT(AI != AE); const ir::Register src1 = this->getRegister(*AI); ++AI;
const ir::Register dst = this->getRegister(&I);
ctx.UPSAMPLE_LONG(getType(ctx, I.getType()), dst, src0, src1);
+ SET_GENIR_DBGINFO(I,1);
break;
}
case GEN_OCL_SADD_SAT_CHAR:
@@ -4024,6 +4103,7 @@ namespace gbe
GBE_ASSERT(AI != AE); const ir::Register src1 = this->getRegister(*AI); ++AI;
const ir::Register dst = this->getRegister(&I);
ctx.ADDSAT(getType(ctx, I.getType()), dst, src0, src1);
+ SET_GENIR_DBGINFO(I,1);
break;
}
case GEN_OCL_UADD_SAT_CHAR:
@@ -4035,6 +4115,7 @@ namespace gbe
GBE_ASSERT(AI != AE); const ir::Register src1 = this->getRegister(*AI); ++AI;
const ir::Register dst = this->getRegister(&I);
ctx.ADDSAT(getUnsignedType(ctx, I.getType()), dst, src0, src1);
+ SET_GENIR_DBGINFO(I,1);
break;
}
case GEN_OCL_SSUB_SAT_CHAR:
@@ -4046,6 +4127,7 @@ namespace gbe
GBE_ASSERT(AI != AE); const ir::Register src1 = this->getRegister(*AI); ++AI;
const ir::Register dst = this->getRegister(&I);
ctx.SUBSAT(getType(ctx, I.getType()), dst, src0, src1);
+ SET_GENIR_DBGINFO(I,1);
break;
}
case GEN_OCL_USUB_SAT_CHAR:
@@ -4057,6 +4139,7 @@ namespace gbe
GBE_ASSERT(AI != AE); const ir::Register src1 = this->getRegister(*AI); ++AI;
const ir::Register dst = this->getRegister(&I);
ctx.SUBSAT(getUnsignedType(ctx, I.getType()), dst, src0, src1);
+ SET_GENIR_DBGINFO(I,1);
break;
}
case GEN_OCL_I64_MAD_SAT:
@@ -4066,6 +4149,7 @@ namespace gbe
GBE_ASSERT(AI != AE); const ir::Register src2 = this->getRegister(*AI); ++AI;
const ir::Register dst = this->getRegister(&I);
ctx.I64MADSAT(getType(ctx, I.getType()), dst, src0, src1, src2);
+ SET_GENIR_DBGINFO(I,1);
break;
}
case GEN_OCL_I64_MAD_SATU:
@@ -4075,6 +4159,7 @@ namespace gbe
GBE_ASSERT(AI != AE); const ir::Register src2 = this->getRegister(*AI); ++AI;
const ir::Register dst = this->getRegister(&I);
ctx.I64MADSAT(getUnsignedType(ctx, I.getType()), dst, src0, src1, src2);
+ SET_GENIR_DBGINFO(I,1);
break;
}
case GEN_OCL_FMAX:
@@ -4090,7 +4175,9 @@ namespace gbe
ctx.GE(getType(ctx, I.getType()), cmp, src0, src1);
else
ctx.LT(getType(ctx, I.getType()), cmp, src0, src1);
+ SET_GENIR_DBGINFO(I,1);
ctx.SEL(getType(ctx, I.getType()), dst, cmp, src0, src1);
+ SET_GENIR_DBGINFO(I,1);
break;
}
case GEN_OCL_HADD: {
@@ -4098,6 +4185,7 @@ namespace gbe
GBE_ASSERT(AI != AE); const ir::Register src1 = this->getRegister(*AI); ++AI;
const ir::Register dst = this->getRegister(&I);
ctx.HADD(getUnsignedType(ctx, I.getType()), dst, src0, src1);
+ SET_GENIR_DBGINFO(I,1);
break;
}
case GEN_OCL_I64HADD:
@@ -4108,6 +4196,7 @@ namespace gbe
const ir::Register src1 = this->getRegister(*(AI++));
const ir::Register dst = this->getRegister(&I);
ctx.I64HADD(ir::TYPE_U64, dst, src0, src1);
+ SET_GENIR_DBGINFO(I,1);
break;
}
case GEN_OCL_RHADD: {
@@ -4115,6 +4204,7 @@ namespace gbe
GBE_ASSERT(AI != AE); const ir::Register src1 = this->getRegister(*AI); ++AI;
const ir::Register dst = this->getRegister(&I);
ctx.RHADD(getUnsignedType(ctx, I.getType()), dst, src0, src1);
+ SET_GENIR_DBGINFO(I,1);
break;
}
case GEN_OCL_I64RHADD:
@@ -4125,10 +4215,11 @@ namespace gbe
const ir::Register src1 = this->getRegister(*(AI++));
const ir::Register dst = this->getRegister(&I);
ctx.I64RHADD(ir::TYPE_U64, dst, src0, src1);
+ SET_GENIR_DBGINFO(I,1);
break;
}
#define DEF(DST_TYPE, SRC_TYPE) \
- { ctx.SAT_CVT(DST_TYPE, SRC_TYPE, getRegister(&I), getRegister(I.getOperand(0))); break; }
+ { ctx.SAT_CVT(DST_TYPE, SRC_TYPE, getRegister(&I), getRegister(I.getOperand(0)));SET_GENIR_DBGINFO(I,1); break; }
case GEN_OCL_SAT_CONV_U8_TO_I8:
DEF(ir::TYPE_S8, ir::TYPE_U8);
case GEN_OCL_SAT_CONV_I16_TO_I8:
@@ -4191,9 +4282,11 @@ namespace gbe
DEF(ir::TYPE_U32, ir::TYPE_HALF);
case GEN_OCL_CONV_F16_TO_F32:
ctx.F16TO32(ir::TYPE_FLOAT, ir::TYPE_U16, getRegister(&I), getRegister(I.getOperand(0)));
+ SET_GENIR_DBGINFO(I,1);
break;
case GEN_OCL_CONV_F32_TO_F16:
ctx.F32TO16(ir::TYPE_U16, ir::TYPE_FLOAT, getRegister(&I), getRegister(I.getOperand(0)));
+ SET_GENIR_DBGINFO(I,1);
break;
#undef DEF
@@ -4208,12 +4301,14 @@ namespace gbe
{
const ir::Register dst = this->getRegister(&I);
ctx.ALU0(ir::OP_SIMD_SIZE, getType(ctx, I.getType()), dst);
+ SET_GENIR_DBGINFO(I,1);
break;
}
case GEN_OCL_SIMD_ID:
{
const ir::Register dst = this->getRegister(&I);
ctx.ALU0(ir::OP_SIMD_ID, getType(ctx, I.getType()), dst);
+ SET_GENIR_DBGINFO(I,1);
break;
}
case GEN_OCL_SIMD_SHUFFLE:
@@ -4222,6 +4317,7 @@ namespace gbe
const ir::Register src1 = this->getRegister(*AI); ++AI;
const ir::Register dst = this->getRegister(&I);
ctx.SIMD_SHUFFLE(getType(ctx, I.getType()), dst, src0, src1);
+ SET_GENIR_DBGINFO(I,1);
break;
}
default: break;
@@ -4276,15 +4372,20 @@ namespace gbe
ir::ImmediateIndex stepImm = ctx.newIntegerImmediate(step, ir::TYPE_U32);
ir::Register stepReg = ctx.reg(ctx.getPointerFamily());
ctx.LOADI(ir::TYPE_U32, stepReg, stepImm);
+ SET_GENIR_DBGINFO(I,1);
ctx.ADD(ir::TYPE_U32, stack, stack, stepReg);
+ SET_GENIR_DBGINFO(I,1);
ctx.getFunction().pushStackSize(step);
}
}
// Set the destination register properly
ctx.MOV(imm.getType(), dst, stack);
+ SET_GENIR_DBGINFO(I,1);
ctx.LOADI(imm.getType(), reg, immIndex);
+ SET_GENIR_DBGINFO(I,1);
ctx.ADD(imm.getType(), stack, stack, reg);
+ SET_GENIR_DBGINFO(I,1);
ctx.getFunction().pushStackSize(elementSize);
}
@@ -4344,7 +4445,9 @@ namespace gbe
addr = ctx.reg(pointerFamily);
ctx.LOADI(immType, offset, immIndex);
+ SET_GENIR_DBGINFO(llvmValues,3);
ctx.ADD(immType, addr, ptr, offset);
+ SET_GENIR_DBGINFO(llvmValues,3);
}
// Emit the instruction
@@ -4352,6 +4455,7 @@ namespace gbe
ctx.LOAD(type, tuple, addr, addrSpace, perMsgNum, dwAligned, fixedBTI, bti);
else
ctx.STORE(type, tuple, addr, addrSpace, perMsgNum, dwAligned, fixedBTI, bti);
+ SET_GENIR_DBGINFO(llvmValues,3);
}
}
@@ -4391,9 +4495,12 @@ namespace gbe
if (isLoad) {
ctx.LOAD(ir::TYPE_U8, byteTuple, ptr, addrSpace, byteSize, dwAligned, fixedBTI, bti);
+ SET_GENIR_DBGINFO(llvmValues,3);
ctx.BITCAST(type, ir::TYPE_U8, tuple, byteTuple, elemNum, byteSize);
+ SET_GENIR_DBGINFO(llvmValues,3);
} else {
ctx.BITCAST(ir::TYPE_U8, type, byteTuple, tuple, byteSize, elemNum);
+ SET_GENIR_DBGINFO(llvmValues,3);
// FIXME: byte scatter does not handle correctly vector store, after fix that,
// we can directly use on store instruction like:
// ctx.STORE(ir::TYPE_U8, byteTuple, ptr, addrSpace, byteSize, dwAligned, fixedBTI, bti);
@@ -4409,9 +4516,12 @@ namespace gbe
immIndex = ctx.newImmediate(int32_t(elemID));
addr = ctx.reg(pointerFamily);
ctx.LOADI(ir::TYPE_S32, offset, immIndex);
+ SET_GENIR_DBGINFO(llvmValues,3);
ctx.ADD(ir::TYPE_S32, addr, ptr, offset);
+ SET_GENIR_DBGINFO(llvmValues,3);
}
ctx.STORE(type, addr, addrSpace, dwAligned, fixedBTI, bti, reg);
+ SET_GENIR_DBGINFO(llvmValues,3);
}
}
}
@@ -4445,6 +4555,7 @@ namespace gbe
ir::ImmediateIndex immIndex = ctx.newImmediate((uint32_t)index);
btiReg = ctx.reg(ir::FAMILY_DWORD);
ctx.LOADI(ir::TYPE_U32, btiReg, immIndex);
+ SET_GENIR_DBGINFO(I,1);
} else {
addrSpace = ir::MEM_MIXED;
btiReg = this->getRegister(bti);
@@ -4460,8 +4571,10 @@ namespace gbe
// FIXME: avoid subtraction zero at this stage is not a good idea,
// but later ArgumentLower pass need to match exact load/addImm pattern
// so, I avoid subtracting zero base to satisfy ArgumentLower pass.
- if (!zeroBase)
+ if (!zeroBase) {
ctx.SUB(ir::TYPE_U32, ptr, pointer, baseReg);
+ SET_GENIR_DBGINFO(I,1);
+ }
else
ptr = pointer;
@@ -4480,6 +4593,7 @@ namespace gbe
ctx.LOAD(type, ptr, addrSpace, dwAligned, fixedBTI, btiReg, values);
else
ctx.STORE(type, ptr, addrSpace, dwAligned, fixedBTI, btiReg, values);
+ SET_GENIR_DBGINFO(I,1);
}
// A vector type requires to build a tuple
else {
@@ -4525,6 +4639,7 @@ namespace gbe
ctx.LOAD(type, tuple, ptr, addrSpace, elemNum, dwAligned, fixedBTI, btiReg);
else
ctx.STORE(type, tuple, ptr, addrSpace, elemNum, dwAligned, fixedBTI, btiReg);
+ SET_GENIR_DBGINFO(I,1);
}
// Not supported by the hardware. So, we split the message and we use
// strided loads and stores
@@ -4551,12 +4666,15 @@ namespace gbe
immIndex = ctx.newImmediate(int32_t(elemID * elemSize));
addr = ctx.reg(pointerFamily);
ctx.LOADI(ir::TYPE_S32, offset, immIndex);
+ SET_GENIR_DBGINFO(I,1);
ctx.ADD(ir::TYPE_S32, addr, ptr, offset);
+ SET_GENIR_DBGINFO(I,1);
}
if (isLoad)
ctx.LOAD(type, addr, addrSpace, dwAligned, fixedBTI, btiReg, reg);
else
ctx.STORE(type, addr, addrSpace, dwAligned, fixedBTI, btiReg, reg);
+ SET_GENIR_DBGINFO(I,1);
}
}
}
--
1.9.1
More information about the Beignet
mailing list