[Beignet] [PATCH 7/7] refine pass debug info from llvm ir to gen insn
Bai Yannan
yannan.bai at intel.com
Fri Sep 18 02:01:57 PDT 2015
Add line and col to ctx to pass debug infomation
Signed-off-by: Bai Yannan <yannan.bai at intel.com>
Signed-off-by: Lv Meng <meng.lv at intel.com>
---
backend/src/backend/gen_context.cpp | 93 +++++++++++-----------
backend/src/backend/gen_encoder.cpp | 24 +++---
backend/src/backend/gen_encoder.hpp | 7 +-
backend/src/ir/context.cpp | 2 +
backend/src/ir/context.hpp | 3 +
backend/src/llvm/llvm_gen_backend.cpp | 142 ++++++----------------------------
backend/src/llvm/llvm_to_gen.cpp | 4 +-
7 files changed, 93 insertions(+), 182 deletions(-)
diff --git a/backend/src/backend/gen_context.cpp b/backend/src/backend/gen_context.cpp
index 43c0b25..18a02a0 100644
--- a/backend/src/backend/gen_context.cpp
+++ b/backend/src/backend/gen_context.cpp
@@ -92,11 +92,6 @@ namespace gbe
}
#define OCL_PROFILING (bool)(getenv("OCL_PROFILING")[0]-48)
-#define SET_GENINSN_DBGINFO(INSN) \
- if(INSN.dbginfo.hasdbginfo) \
- p->setDbginfo(INSN.dbginfo.line,INSN.dbginfo.col);\
- else p->setDbginfo(0,0)
-
void GenContext::emitInstructionStream(void) {
// Emit Gen ISA
for (auto &block : *sel->blockList)
@@ -106,6 +101,9 @@ namespace gbe
// no more virtual register here in that part of the code generation
GBE_ASSERT(insn.state.physicalFlag);
p->curr = insn.state;
+ //meng
+ p->line = insn.dbginfo.line;
+ p->col = insn.dbginfo.col;
switch (opcode) {
#define DECL_SELECTION_IR(OPCODE, FAMILY) \
case SEL_OP_##OPCODE: this->emit##FAMILY(insn); break;
@@ -119,7 +117,6 @@ namespace gbe
instruction prefetcher prefetch into an invalide page */
for(int i = 0; i < 8; i++)
p->NOP();
- p->setDbginfo(0,0);
}
bool GenContext::patchBranches(void) {
@@ -255,7 +252,7 @@ namespace gbe
void GenContext::emitLabelInstruction(const SelectionInstruction &insn) {
const ir::LabelIndex label(insn.index);
this->labelPos.insert(std::make_pair(label, p->store.size()));
- SET_GENINSN_DBGINFO(insn);
+ //SET_GENINSN_DBGINFO(insn);
}
void GenContext::emitUnaryInstruction(const SelectionInstruction &insn) {
@@ -330,7 +327,7 @@ namespace gbe
break;
default: NOT_IMPLEMENTED;
}
- SET_GENINSN_DBGINFO(insn);
+ //SET_GENINSN_DBGINFO(insn);
}
void GenContext::emitUnaryWithTempInstruction(const SelectionInstruction &insn) {
@@ -489,7 +486,7 @@ namespace gbe
default:
NOT_IMPLEMENTED;
}
- SET_GENINSN_DBGINFO(insn);
+ //SET_GENINSN_DBGINFO(insn);
}
void GenContext::emitBinaryWithTempInstruction(const SelectionInstruction &insn) {
@@ -590,7 +587,7 @@ namespace gbe
default:
NOT_IMPLEMENTED;
}
- SET_GENINSN_DBGINFO(insn);
+ //SET_GENINSN_DBGINFO(insn);
}
void GenContext::emitSimdShuffleInstruction(const SelectionInstruction &insn) {
@@ -682,7 +679,7 @@ namespace gbe
break;
default: NOT_IMPLEMENTED;
}
- SET_GENINSN_DBGINFO(insn);
+ //SET_GENINSN_DBGINFO(insn);
}
void GenContext::collectShifter(GenRegister dest, GenRegister src) {
@@ -777,7 +774,7 @@ namespace gbe
}
storeTopHalf(dest, e);
storeBottomHalf(dest, f);
- SET_GENINSN_DBGINFO(insn);
+ //SET_GENINSN_DBGINFO(insn);
}
void GenContext::emitI64MADSATInstruction(const SelectionInstruction &insn) {
@@ -909,7 +906,7 @@ namespace gbe
}
storeTopHalf(dest, g);
storeBottomHalf(dest, h);
- SET_GENINSN_DBGINFO(insn);
+ //SET_GENINSN_DBGINFO(insn);
}
void GenContext::emitI64HADDInstruction(const SelectionInstruction &insn) {
@@ -937,7 +934,7 @@ namespace gbe
p->OR(c, c, d);
storeBottomHalf(dest, a);
storeTopHalf(dest, c);
- SET_GENINSN_DBGINFO(insn);
+ //SET_GENINSN_DBGINFO(insn);
}
void GenContext::emitI64RHADDInstruction(const SelectionInstruction &insn) {
@@ -968,7 +965,7 @@ namespace gbe
p->OR(c, c, d);
storeBottomHalf(dest, a);
storeTopHalf(dest, c);
- SET_GENINSN_DBGINFO(insn);
+ //SET_GENINSN_DBGINFO(insn);
}
void GenContext::emitI64ShiftInstruction(const SelectionInstruction &insn) {
@@ -1075,7 +1072,7 @@ namespace gbe
default:
NOT_IMPLEMENTED;
}
- SET_GENINSN_DBGINFO(insn);
+ //SET_GENINSN_DBGINFO(insn);
}
void GenContext::setFlag(GenRegister flagReg, GenRegister src) {
p->push();
@@ -1231,7 +1228,7 @@ namespace gbe
p->OR(dest, dest, GenRegister::immud(0x80000000));
p->pop();
}
- SET_GENINSN_DBGINFO(insn);
+ //SET_GENINSN_DBGINFO(insn);
}
@@ -1271,7 +1268,7 @@ namespace gbe
}
storeTopHalf(dst, high);
storeBottomHalf(dst, low);
- SET_GENINSN_DBGINFO(insn);
+ //SET_GENINSN_DBGINFO(insn);
}
void GenContext::emitI64CompareInstruction(const SelectionInstruction &insn) {
@@ -1352,7 +1349,7 @@ namespace gbe
p->curr.execWidth = 1;
p->MOV(GenRegister::flag(flag, subFlag), f1);
p->pop();
- SET_GENINSN_DBGINFO(insn);
+ //SET_GENINSN_DBGINFO(insn);
}
void GenContext::emitI64SATADDInstruction(const SelectionInstruction &insn) {
@@ -1402,7 +1399,7 @@ namespace gbe
p->pop();
storeTopHalf(dst, a);
storeBottomHalf(dst, b);
- SET_GENINSN_DBGINFO(insn);
+ //SET_GENINSN_DBGINFO(insn);
}
void GenContext::emitI64SATSUBInstruction(const SelectionInstruction &insn) {
@@ -1451,7 +1448,7 @@ namespace gbe
p->pop();
storeTopHalf(dst, a);
storeBottomHalf(dst, b);
- SET_GENINSN_DBGINFO(insn);
+ //SET_GENINSN_DBGINFO(insn);
}
void GenContext::loadTopHalf(GenRegister dest, GenRegister src) {
@@ -1549,7 +1546,7 @@ namespace gbe
p->pop();
storeTopHalf(dest, e);
storeBottomHalf(dest, a);
- SET_GENINSN_DBGINFO(insn);
+ //SET_GENINSN_DBGINFO(insn);
}
void GenContext::emitI64DIVREMInstruction(const SelectionInstruction &insn) {
@@ -1703,7 +1700,7 @@ namespace gbe
storeTopHalf(dest, a);
storeBottomHalf(dest, b);
}
- SET_GENINSN_DBGINFO(insn);
+ //SET_GENINSN_DBGINFO(insn);
}
void GenContext::emitTernaryInstruction(const SelectionInstruction &insn) {
@@ -1715,17 +1712,17 @@ namespace gbe
case SEL_OP_MAD: p->MAD(dst, src0, src1, src2); break;
default: NOT_IMPLEMENTED;
}
- SET_GENINSN_DBGINFO(insn);
+ //SET_GENINSN_DBGINFO(insn);
}
void GenContext::emitNoOpInstruction(const SelectionInstruction &insn) {
p->NOP();
- SET_GENINSN_DBGINFO(insn);
+ //SET_GENINSN_DBGINFO(insn);
}
void GenContext::emitWaitInstruction(const SelectionInstruction &insn) {
p->WAIT();
- SET_GENINSN_DBGINFO(insn);
+ //SET_GENINSN_DBGINFO(insn);
}
void GenContext::emitBarrierInstruction(const SelectionInstruction &insn) {
@@ -1752,14 +1749,14 @@ namespace gbe
// Now we wait for the other threads
p->WAIT();
p->pop();
- SET_GENINSN_DBGINFO(insn);
+ //SET_GENINSN_DBGINFO(insn);
}
void GenContext::emitFenceInstruction(const SelectionInstruction &insn) {
const GenRegister dst = ra->genReg(insn.dst(0));
p->FENCE(dst);
p->MOV(dst, dst);
- SET_GENINSN_DBGINFO(insn);
+ //SET_GENINSN_DBGINFO(insn);
}
void GenContext::emitMathInstruction(const SelectionInstruction &insn) {
@@ -1771,7 +1768,7 @@ namespace gbe
p->MATH(dst, function, src0, src1);
} else
p->MATH(dst, function, src0);
- SET_GENINSN_DBGINFO(insn);
+ //SET_GENINSN_DBGINFO(insn);
}
void GenContext::emitCompareInstruction(const SelectionInstruction &insn) {
@@ -1785,7 +1782,7 @@ namespace gbe
const GenRegister dst = ra->genReg(insn.dst(0));
p->SEL_CMP(insn.extra.function, dst, src0, src1);
}
- SET_GENINSN_DBGINFO(insn);
+ //SET_GENINSN_DBGINFO(insn);
}
void GenContext::emitAtomicInstruction(const SelectionInstruction &insn) {
@@ -1811,7 +1808,7 @@ namespace gbe
p->pop();
afterMessage(insn, bti, flagTemp, jip0);
}
- SET_GENINSN_DBGINFO(insn);
+ //SET_GENINSN_DBGINFO(insn);
}
void GenContext::emitIndirectMoveInstruction(const SelectionInstruction &insn) {
@@ -1855,7 +1852,7 @@ namespace gbe
p->MOV(nextDst, indirect_src);
p->pop();
}
- SET_GENINSN_DBGINFO(insn);
+ //SET_GENINSN_DBGINFO(insn);
}
void GenContext::insertJumpPos(const SelectionInstruction &insn) {
@@ -1867,7 +1864,7 @@ namespace gbe
insertJumpPos(insn);
const GenRegister src = ra->genReg(insn.src(0));
p->JMPI(src, insn.extra.longjmp);
- SET_GENINSN_DBGINFO(insn);
+ //SET_GENINSN_DBGINFO(insn);
}
void GenContext::emitEotInstruction(const SelectionInstruction &insn) {
@@ -1878,7 +1875,7 @@ namespace gbe
p->curr.execWidth = 8;
p->EOT(112);
p->pop();
- SET_GENINSN_DBGINFO(insn);
+ //SET_GENINSN_DBGINFO(insn);
}
void GenContext::emitSpillRegInstruction(const SelectionInstruction &insn) {
@@ -1915,7 +1912,7 @@ namespace gbe
this->scratchWrite(msg, scratchOffset + 4*simdWidth, regNum, GEN_TYPE_UD, GEN_SCRATCH_CHANNEL_MODE_DWORD);
}
p->pop();
- SET_GENINSN_DBGINFO(insn);
+ //SET_GENINSN_DBGINFO(insn);
}
void GenContext::emitUnSpillRegInstruction(const SelectionInstruction &insn) {
@@ -1944,7 +1941,7 @@ namespace gbe
storeTopHalf(dst, payload);
}
p->pop();
- SET_GENINSN_DBGINFO(insn);
+ //SET_GENINSN_DBGINFO(insn);
}
void GenContext::emitRead64Instruction(const SelectionInstruction &insn) {
@@ -1969,7 +1966,7 @@ namespace gbe
p->pop();
afterMessage(insn, bti, tmp, jip0);
}
- SET_GENINSN_DBGINFO(insn);
+ //SET_GENINSN_DBGINFO(insn);
}
unsigned GenContext::beforeMessage(const SelectionInstruction &insn, GenRegister bti, GenRegister tmp, unsigned desc) {
const GenRegister flagReg = GenRegister::flag(insn.state.flag, insn.state.subFlag);
@@ -2038,7 +2035,7 @@ namespace gbe
p->pop();
afterMessage(insn, bti, tmp, jip0);
}
- SET_GENINSN_DBGINFO(insn);
+ //SET_GENINSN_DBGINFO(insn);
}
void GenContext::emitWrite64Instruction(const SelectionInstruction &insn) {
@@ -2062,7 +2059,7 @@ namespace gbe
p->pop();
afterMessage(insn, bti, tmp, jip0);
}
- SET_GENINSN_DBGINFO(insn);
+ //SET_GENINSN_DBGINFO(insn);
}
void GenContext::emitUntypedWriteInstruction(const SelectionInstruction &insn) {
@@ -2085,7 +2082,7 @@ namespace gbe
p->pop();
afterMessage(insn, bti, tmp, jip0);
}
- SET_GENINSN_DBGINFO(insn);
+ //SET_GENINSN_DBGINFO(insn);
}
void GenContext::emitByteGatherInstruction(const SelectionInstruction &insn) {
@@ -2110,7 +2107,7 @@ namespace gbe
p->pop();
afterMessage(insn, bti, tmp, jip0);
}
- SET_GENINSN_DBGINFO(insn);
+ //SET_GENINSN_DBGINFO(insn);
}
void GenContext::emitByteScatterInstruction(const SelectionInstruction &insn) {
@@ -2134,7 +2131,7 @@ namespace gbe
p->pop();
afterMessage(insn, bti, tmp, jip0);
}
- SET_GENINSN_DBGINFO(insn);
+ //SET_GENINSN_DBGINFO(insn);
}
@@ -2143,7 +2140,7 @@ namespace gbe
for(uint32_t i = 0; i < insn.dstNum; i++) {
p->MOV(ra->genReg(insn.dst(i)), GenRegister::splitReg(src, insn.extra.elem, i));
}
- SET_GENINSN_DBGINFO(insn);
+ //SET_GENINSN_DBGINFO(insn);
}
void GenContext::emitPackByteInstruction(const SelectionInstruction &insn) {
@@ -2166,7 +2163,7 @@ namespace gbe
}
}
p->pop();
- SET_GENINSN_DBGINFO(insn);
+ //SET_GENINSN_DBGINFO(insn);
}
void GenContext::emitUnpackLongInstruction(const SelectionInstruction &insn) {
@@ -2182,7 +2179,7 @@ namespace gbe
const GenRegister src = ra->genReg(insn.src(0));
const uint32_t bti = insn.getbti();
p->DWORD_GATHER(dst, src, bti);
- SET_GENINSN_DBGINFO(insn);
+ //SET_GENINSN_DBGINFO(insn);
}
void GenContext::emitSampleInstruction(const SelectionInstruction &insn) {
@@ -2193,7 +2190,7 @@ namespace gbe
const unsigned int msgLen = insn.extra.rdmsglen;
uint32_t simdWidth = p->curr.execWidth;
p->SAMPLE(dst, msgPayload, msgLen, false, bti, sampler, simdWidth, -1, 0, insn.extra.isLD, insn.extra.isUniform);
- SET_GENINSN_DBGINFO(insn);
+ //SET_GENINSN_DBGINFO(insn);
}
void GenContext::scratchWrite(const GenRegister header, uint32_t offset, uint32_t reg_num, uint32_t reg_type, uint32_t channel_mode) {
@@ -2231,7 +2228,7 @@ namespace gbe
const GenRegister header = GenRegister::retype(ra->genReg(insn.src(0)), GEN_TYPE_UD);
const uint32_t bti = insn.getbti();
p->TYPED_WRITE(header, true, bti);
- SET_GENINSN_DBGINFO(insn);
+ //SET_GENINSN_DBGINFO(insn);
}
void GenContext::setA0Content(uint16_t new_a0[16], uint16_t max_offset, int sz) {
@@ -2370,6 +2367,8 @@ namespace gbe
std::memcpy(genKernel->insns, &p->store[0], genKernel->insnNum * sizeof(GenInstruction));
if (OCL_OUTPUT_ASM)
outputAssembly(stdout, genKernel);
+ if (OCL_PROFILING)
+ outputAssembly(stdout, genKernel);
if (this->asmFileName) {
FILE *asmDumpStream = fopen(this->asmFileName, "a");
diff --git a/backend/src/backend/gen_encoder.cpp b/backend/src/backend/gen_encoder.cpp
index 0f50c35..8a19cb9 100644
--- a/backend/src/backend/gen_encoder.cpp
+++ b/backend/src/backend/gen_encoder.cpp
@@ -50,7 +50,6 @@
#include "backend/gen_encoder.hpp"
#include <cstring>
-#include <map>
namespace gbe
@@ -598,6 +597,11 @@ namespace gbe
std::memset(&insn, 0, sizeof(GenCompactInstruction));
insn.bits1.opcode = opcode;
this->store.push_back(insn.low);
+ //meng
+ GenInsnDBGInfo dginfo;
+ dginfo.srcline = line;
+ dginfo.srccol = col;
+ storedbg.push_back(dginfo);
return (GenCompactInstruction *)&this->store.back();
}
@@ -607,6 +611,12 @@ namespace gbe
insn.header.opcode = opcode;
this->store.push_back(insn.low);
this->store.push_back(insn.high);
+ //meng
+ GenInsnDBGInfo dginfo;
+ dginfo.srcline = line;
+ dginfo.srccol = col;
+ storedbg.push_back(dginfo);
+ storedbg.push_back(dginfo);
return (GenNativeInstruction *)(&this->store.back()-1);
}
@@ -1299,17 +1309,5 @@ namespace gbe
insn->header.destreg_or_condmod = GEN_SFID_THREAD_SPAWNER;
}
- void GenEncoder::setDbginfo(uint32_t line,uint32_t col) {
- GenInsnDBGInfo gd;
- for(int i = 0; i<this->store.size(); i++)
- {
- auto it = this->storedbg.find(i);
- if(it != this->storedbg.end())
- continue;
- gd.srcline = line;
- gd.srccol = col;
- storedbg[i] = gd;
- }
- }
} /* namespace gbe */
diff --git a/backend/src/backend/gen_encoder.hpp b/backend/src/backend/gen_encoder.hpp
index 9797abc..d727720 100644
--- a/backend/src/backend/gen_encoder.hpp
+++ b/backend/src/backend/gen_encoder.hpp
@@ -57,7 +57,6 @@
#include "sys/vector.hpp"
#include <cassert>
#include "src/cl_device_data.h"
-#include <map>
namespace gbe
{
@@ -89,6 +88,9 @@ namespace gbe
uint32_t deviceID;
/*! simd width for this codegen */
uint32_t simdWidth;
+ //meng
+ uint32_t line;
+ uint32_t col;
////////////////////////////////////////////////////////////////////////
// Encoding functions
////////////////////////////////////////////////////////////////////////
@@ -258,8 +260,7 @@ namespace gbe
virtual void alu3(uint32_t opcode, GenRegister dst,
GenRegister src0, GenRegister src1, GenRegister src2) = 0;
public:
- void setDbginfo(uint32_t line, uint32_t col);
- std::map<int, GenInsnDBGInfo> storedbg;
+ std::vector<GenInsnDBGInfo> storedbg;
};
void alu1(GenEncoder *p, uint32_t opcode, GenRegister dst,
diff --git a/backend/src/ir/context.cpp b/backend/src/ir/context.cpp
index 2412fe9..8e18be3 100644
--- a/backend/src/ir/context.cpp
+++ b/backend/src/ir/context.cpp
@@ -159,6 +159,8 @@ namespace ir {
// Append the instruction in the stream
Instruction *insnPtr = fn->newInstruction(insn);
bb->append(*insnPtr);
+ //meng
+ insnPtr->setDBGInfo(line,col);
#if GBE_DEBUG
std::string whyNot;
if(getUnit().getValid())
diff --git a/backend/src/ir/context.hpp b/backend/src/ir/context.hpp
index 54265d0..c38c99f 100644
--- a/backend/src/ir/context.hpp
+++ b/backend/src/ir/context.hpp
@@ -209,6 +209,9 @@ namespace ir {
}
void appendSurface(uint8_t bti, Register reg) { fn->appendSurface(bti, reg); }
+ //meng
+ uint32_t line;
+ uint32_t col;
protected:
/*! A block must be started with a label */
void startBlock(void);
diff --git a/backend/src/llvm/llvm_gen_backend.cpp b/backend/src/llvm/llvm_gen_backend.cpp
index e3b6b13..b426f82 100644
--- a/backend/src/llvm/llvm_gen_backend.cpp
+++ b/backend/src/llvm/llvm_gen_backend.cpp
@@ -202,11 +202,7 @@ using namespace llvm;
if(OCL_PROFILING){ \
llvm::DebugLoc dg; \
GET_INSN_DBGLOC##FLAG(I); \
- gbe::ir::BasicBlock * bb = ctx.getBlock(); \
- if(bb)\
- for(gbe::ir::Instruction *in = bb->getFirstInstruction(); in!=bb->getLastInstruction(); in=bb->getSuccessorInstruction(in) )\
- if(!in->DBGInfo.hasDBGInfo) in->setDBGInfo(dg.getLine(), dg.getCol());\
- }
+ ctx.line = dg.getLine(), ctx.col = dg.getCol();}
// end define SET_GENIR_DBGINFO
#define GET_PRE_LOADI_DBGINFO \
if(OCL_PROFILING) { \
@@ -1869,6 +1865,7 @@ namespace gbe
void GenWriter::emitMovForPHI(BasicBlock *curr, BasicBlock *succ) {
for (BasicBlock::iterator I = succ->begin(); isa<PHINode>(I); ++I) {
+ SET_GENIR_DBGINFO(I,2);
PHINode *PN = cast<PHINode>(I);
Value *IV = PN->getIncomingValueForBlock(curr);
Type *llvmType = PN->getType();
@@ -1888,11 +1885,9 @@ namespace gbe
isa<UndefValue>(extractConstantElem(CPV, 0)))
continue;
ctx.MOV(type, dst, getRegister(CP));
- SET_GENIR_DBGINFO(PN,2);
} else if (regTranslator.valueExists(IV,0) || dyn_cast<Constant>(IV)) {
const ir::Register src = this->getRegister(IV);
ctx.MOV(type, dst, src);
- SET_GENIR_DBGINFO(PN,2);
}
assert(!ctx.getBlock()->undefPhiRegs.contains(dst));
ctx.getBlock()->definedPhiRegs.insert(dst);
@@ -2827,6 +2822,7 @@ namespace gbe
void GenWriter::regAllocateReturnInst(ReturnInst &I) {}
void GenWriter::emitReturnInst(ReturnInst &I) {
+ SET_GENIR_DBGINFO(I,1);
const ir::Function &fn = ctx.getFunction();
GBE_ASSERTM(fn.outputNum() <= 1, "no more than one value can be returned");
if (fn.outputNum() == 1 && I.getNumOperands() > 0) {
@@ -2834,10 +2830,8 @@ namespace gbe
const ir::Register src = this->getRegister(I.getOperand(0));
const ir::RegisterFamily family = fn.getRegisterFamily(dst);
ctx.MOV(ir::getType(family), dst, src);
- SET_GENIR_DBGINFO(I,1);
}
ctx.RET();
- //SET_GENIR_DBGINFO(I, 1);
}
void GenWriter::regAllocateBinaryOperator(Instruction &I) {
@@ -2865,7 +2859,7 @@ namespace gbe
const ir::Register dst = this->getRegister(&I);
const ir::Register src0 = this->getRegister(I.getOperand(0));
const ir::Register src1 = this->getRegister(I.getOperand(1));
- bool isSupported = true;
+ SET_GENIR_DBGINFO(I,1);
switch (I.getOpcode()) {
case Instruction::Add:
@@ -2886,10 +2880,8 @@ namespace gbe
case Instruction::Shl: ctx.SHL(type, dst, src0, src1); break;
case Instruction::LShr: ctx.SHR(getUnsignedType(ctx, I.getType()), dst, src0, src1); break;
case Instruction::AShr: ctx.ASR(type, dst, src0, src1); break;
- default: isSupported = false; NOT_SUPPORTED;
+ default: NOT_SUPPORTED;
}
- if(isSupported)
- SET_GENIR_DBGINFO(I,1);
}
void GenWriter::regAllocateICmpInst(ICmpInst &I) {
@@ -2925,7 +2917,7 @@ namespace gbe
const ir::Register src1 = this->getRegister(I.getOperand(1));
// We must invert the condition to simplify the branch code
- bool isSupported = true;
+ SET_GENIR_DBGINFO(I,1);
if (conditionSet.find(&I) != conditionSet.end()) {
switch (I.getPredicate()) {
case ICmpInst::ICMP_EQ: ctx.NE(type, dst, src0, src1); break;
@@ -2938,7 +2930,7 @@ namespace gbe
case ICmpInst::ICMP_SLT: ctx.GE(signedType, dst, src0, src1); break;
case ICmpInst::ICMP_UGT: ctx.LE(unsignedType, dst, src0, src1); break;
case ICmpInst::ICMP_SGT: ctx.LE(signedType, dst, src0, src1); break;
- default: isSupported = false; NOT_SUPPORTED;
+ default: NOT_SUPPORTED;
}
}
// Nothing special to do
@@ -2954,11 +2946,9 @@ namespace gbe
case ICmpInst::ICMP_SLT: ctx.LT(signedType, dst, src0, src1); break;
case ICmpInst::ICMP_UGT: ctx.GT(unsignedType, dst, src0, src1); break;
case ICmpInst::ICMP_SGT: ctx.GT(signedType, dst, src0, src1); break;
- default: isSupported = false;NOT_SUPPORTED;
+ default: NOT_SUPPORTED;
}
}
- if(isSupported)
- SET_GENIR_DBGINFO(I,1);
}
void GenWriter::regAllocateFCmpInst(FCmpInst &I) {
@@ -2978,8 +2968,8 @@ namespace gbe
const ir::Register src1 = this->getRegister(I.getOperand(1));
const ir::Register tmp = ctx.reg(getFamily(ctx, I.getType()));
Value *cv = ConstantInt::get(I.getType(), 1);
- bool isSupported = true;
+ SET_GENIR_DBGINFO(I,1);
switch (I.getPredicate()) {
case ICmpInst::FCMP_OEQ: ctx.EQ(type, dst, src0, src1); break;
case ICmpInst::FCMP_ONE: ctx.NE(type, dst, src0, src1); break;
@@ -3005,47 +2995,38 @@ namespace gbe
ctx.NE(type, dst, src0, src0);
else {
ctx.ORD(type, tmp, src0, src1);
- SET_GENIR_DBGINFO(I,1);
ctx.XOR(insnType, dst, tmp, getRegister(cv)); //TODO: Use NOT directly
}
break;
case ICmpInst::FCMP_UEQ:
ctx.NE(type, tmp, src0, src1);
- SET_GENIR_DBGINFO(I,1);
ctx.XOR(insnType, dst, tmp, getRegister(cv));
break;
case ICmpInst::FCMP_UGT:
ctx.LE(type, tmp, src0, src1);
- SET_GENIR_DBGINFO(I,1);
ctx.XOR(insnType, dst, tmp, getRegister(cv));
break;
case ICmpInst::FCMP_UGE:
ctx.LT(type, tmp, src0, src1);
- SET_GENIR_DBGINFO(I,1);
ctx.XOR(insnType, dst, tmp, getRegister(cv));
break;
case ICmpInst::FCMP_ULT:
ctx.GE(type, tmp, src0, src1);
- SET_GENIR_DBGINFO(I,1);
ctx.XOR(insnType, dst, tmp, getRegister(cv));
break;
case ICmpInst::FCMP_ULE:
ctx.GT(type, tmp, src0, src1);
- SET_GENIR_DBGINFO(I,1);
ctx.XOR(insnType, dst, tmp, getRegister(cv));
break;
case ICmpInst::FCMP_UNE:
ctx.EQ(type, tmp, src0, src1);
- SET_GENIR_DBGINFO(I,1);
ctx.XOR(insnType, dst, tmp, getRegister(cv));
break;
case ICmpInst::FCMP_TRUE:
ctx.MOV(insnType, dst, getRegister(cv));
break;
- default: isSupported = false; NOT_SUPPORTED;
+ default: NOT_SUPPORTED;
}
- if(isSupported)
- SET_GENIR_DBGINFO(I,1);
}
void GenWriter::regAllocateCastInst(CastInst &I) {
@@ -3100,6 +3081,7 @@ namespace gbe
}
void GenWriter::emitCastInst(CastInst &I) {
+ SET_GENIR_DBGINFO(I,1);
switch (I.getOpcode())
{
case Instruction::PtrToInt:
@@ -3114,7 +3096,6 @@ namespace gbe
const ir::Register dst = this->getRegister(&I);
const ir::Register src = this->getRegister(srcValue);
ctx.CVT(getType(ctx, dstType), getType(ctx, srcType), dst, src);
- SET_GENIR_DBGINFO(I,1);
}
}
break;
@@ -3150,7 +3131,6 @@ namespace gbe
const ir::Tuple dstTuple = ctx.arrayTuple(&dstTupleData[0], dstElemNum);
ctx.BITCAST(dstType, srcType, dstTuple, srcTuple, dstElemNum, srcElemNum);
- SET_GENIR_DBGINFO(I,1);
}
}
break; // nothing to emit here
@@ -3192,9 +3172,7 @@ namespace gbe
const ir::Register zeroReg = ctx.reg(family);
const ir::Register oneReg = ctx.reg(family);
ctx.LOADI(dstType, zeroReg, zero);
- SET_GENIR_DBGINFO(I,1);
ctx.LOADI(dstType, oneReg, one);
- SET_GENIR_DBGINFO(I,1);
const ir::Register dst = this->getRegister(&I);
const ir::Register src = this->getRegister(I.getOperand(0));
ctx.SEL(dstType, dst, src, oneReg, zeroReg);
@@ -3211,7 +3189,6 @@ namespace gbe
const ir::Register src = this->getRegister(I.getOperand(0));
ctx.CVT(dstType, srcType, dst, src);
}
- SET_GENIR_DBGINFO(I,1);
}
break;
default: NOT_SUPPORTED;
@@ -3277,8 +3254,8 @@ namespace gbe
const ir::Register cond = this->getRegister(I.getOperand(0));
const ir::Register src0 = this->getRegister(I.getOperand(1));
const ir::Register src1 = this->getRegister(I.getOperand(2));
- ctx.SEL(type, dst, cond, src0, src1);
SET_GENIR_DBGINFO(I,1);
+ ctx.SEL(type, dst, cond, src0, src1);
}
void GenWriter::regAllocatePHINode(PHINode &I) {
@@ -3295,8 +3272,8 @@ namespace gbe
const ir::Register dst = this->getRegister(&I);
const ir::Register src = this->getRegister(copy);
- ctx.MOV(type, dst, src);
SET_GENIR_DBGINFO(I,1);
+ ctx.MOV(type, dst, src);
phiMap.insert(std::make_pair(dst, src));
}
@@ -3311,13 +3288,13 @@ namespace gbe
// Inconditional branch. Just check that we jump to a block which is not our
// successor
+ SET_GENIR_DBGINFO(I,1);
if (I.isConditional() == false) {
BasicBlock *target = I.getSuccessor(0);
if (std::next(Function::iterator(bb)) != Function::iterator(target)) {
GBE_ASSERT(labelMap.find(target) != labelMap.end());
const ir::LabelIndex labelIndex = labelMap[target];
ctx.BRA(labelIndex);
- SET_GENIR_DBGINFO(I,1);
}
}
// The LLVM branch has two targets
@@ -3335,7 +3312,6 @@ namespace gbe
const ir::LabelIndex index = labelMap[taken];
const ir::Register reg = this->getRegister(condition);
ctx.BRA(index, reg);
- SET_GENIR_DBGINFO(I,1);
// If non-taken target is the next block, there is nothing to do
BasicBlock *bb = I.getParent();
@@ -3347,9 +3323,7 @@ namespace gbe
GBE_ASSERT(labelMap.find(nonTaken) != labelMap.end());
const ir::LabelIndex untakenIndex = ctx.label();
ctx.LABEL(untakenIndex);
- SET_GENIR_DBGINFO(I,1);
ctx.BRA(labelMap[nonTaken]);
- SET_GENIR_DBGINFO(I,1);
}
}
@@ -3610,8 +3584,8 @@ namespace gbe
GBE_ASSERT(AI != AE);
const ir::Register src = this->getRegister(*AI);
const ir::Register dst = this->getRegister(&I);
- ctx.ALU1(opcode, type, dst, src);
SET_GENIR_DBGINFO(I,1);
+ ctx.ALU1(opcode, type, dst, src);
}
void GenWriter::emitAtomicInst(CallInst &I, CallSite &CS, ir::AtomicOps opcode) {
@@ -3629,6 +3603,7 @@ namespace gbe
ir::Register btiReg;
bool fixedBTI = false;
+ SET_GENIR_DBGINFO(I,1);
if (isa<ConstantInt>(bti)) {
fixedBTI = true;
unsigned index = cast<ConstantInt>(bti)->getZExtValue();
@@ -3636,7 +3611,6 @@ namespace gbe
ir::ImmediateIndex immIndex = ctx.newImmediate((uint32_t)index);
btiReg = ctx.reg(ir::FAMILY_DWORD);
ctx.LOADI(ir::TYPE_U32, btiReg, immIndex);
- SET_GENIR_DBGINFO(I,1);
} else {
addrSpace = ir::MEM_MIXED;
btiReg = this->getRegister(bti);
@@ -3645,7 +3619,6 @@ namespace gbe
const ir::RegisterFamily pointerFamily = ctx.getPointerFamily();
const ir::Register ptr = ctx.reg(pointerFamily);
ctx.SUB(ir::TYPE_U32, ptr, pointer, baseReg);
- SET_GENIR_DBGINFO(I,1);
const ir::Register dst = this->getRegister(&I);
@@ -3661,7 +3634,6 @@ namespace gbe
}
const ir::Tuple srcTuple = ctx.arrayTuple(&src[0], srcNum);
ctx.ATOMIC(opcode, dst, addrSpace, btiReg, fixedBTI, srcTuple);
- SET_GENIR_DBGINFO(I,1);
}
/* append a new sampler. should be called before any reference to
@@ -3691,6 +3663,7 @@ namespace gbe
void GenWriter::emitCallInst(CallInst &I) {
if (Function *F = I.getCalledFunction()) {
+ SET_GENIR_DBGINFO(I,1);
if (F->getIntrinsicID() != 0) {
const ir::Function &fn = ctx.getFunction();
@@ -3707,7 +3680,6 @@ namespace gbe
const ir::Register src = ir::ocl::stackptr;
const ir::RegisterFamily family = fn.getRegisterFamily(dst);
ctx.MOV(ir::getType(family), dst, src);
- SET_GENIR_DBGINFO(I,1);
}
break;
case Intrinsic::stackrestore:
@@ -3716,7 +3688,6 @@ namespace gbe
const ir::Register src = this->getRegister(I.getOperand(0));
const ir::RegisterFamily family = fn.getRegisterFamily(dst);
ctx.MOV(ir::getType(family), dst, src);
- SET_GENIR_DBGINFO(I,1);
}
break;
#if LLVM_VERSION_MINOR >= 2
@@ -3728,9 +3699,7 @@ namespace gbe
const ir::Register src1 = this->getRegister(I.getOperand(1));
const ir::Register src2 = this->getRegister(I.getOperand(2));
ctx.MUL(ir::TYPE_FLOAT, tmp, src0, src1);
- SET_GENIR_DBGINFO(I,1);
ctx.ADD(ir::TYPE_FLOAT, dst, tmp, src2);
- SET_GENIR_DBGINFO(I,1);
}
break;
case Intrinsic::lifetime_start:
@@ -3750,12 +3719,10 @@ namespace gbe
const ir::Register src0 = this->getRegister(I.getOperand(0));
const ir::Register src1 = this->getRegister(I.getOperand(1));
ctx.ADD(dst0Type, dst0, src0, src1);
- SET_GENIR_DBGINFO(I,1);
ir::Register overflow = this->getRegister(&I, 1);
const ir::Type unsignedType = makeTypeUnsigned(dst0Type);
ctx.LT(unsignedType, overflow, dst0, src1);
- SET_GENIR_DBGINFO(I,1);
}
break;
case Intrinsic::usub_with_overflow:
@@ -3767,12 +3734,10 @@ namespace gbe
const ir::Register src0 = this->getRegister(I.getOperand(0));
const ir::Register src1 = this->getRegister(I.getOperand(1));
ctx.SUB(dst0Type, dst0, src0, src1);
- SET_GENIR_DBGINFO(I,1);
ir::Register overflow = this->getRegister(&I, 1);
const ir::Type unsignedType = makeTypeUnsigned(dst0Type);
ctx.GT(unsignedType, overflow, dst0, src0);
- SET_GENIR_DBGINFO(I,1);
}
break;
case Intrinsic::sadd_with_overflow:
@@ -3807,24 +3772,18 @@ namespace gbe
const ir::RegisterFamily family = getFamily(tmpType);
const ir::Register immReg = ctx.reg(family);
ctx.LOADI(ir::TYPE_S32, immReg, imm);
- SET_GENIR_DBGINFO(I,1);
ir::Register tmp0 = ctx.reg(getFamily(tmpType));
ir::Register tmp1 = ctx.reg(getFamily(tmpType));
ir::Register tmp2 = ctx.reg(getFamily(tmpType));
ctx.CVT(tmpType, srcType, tmp0, src);
- SET_GENIR_DBGINFO(I,1);
ctx.ALU1(ir::OP_LZD, tmpType, tmp1, tmp0);
- SET_GENIR_DBGINFO(I,1);
ctx.SUB(tmpType, tmp2, tmp1, immReg);
- SET_GENIR_DBGINFO(I,1);
ctx.CVT(dstType, tmpType, dst, tmp2);
- SET_GENIR_DBGINFO(I,1);
}
else
{
ctx.ALU1(ir::OP_LZD, dstType, dst, src);
- SET_GENIR_DBGINFO(I,1);
}
}
break;
@@ -3836,7 +3795,6 @@ namespace gbe
const ir::Register src1 = this->getRegister(I.getOperand(1));
const ir::Register src2 = this->getRegister(I.getOperand(2));
ctx.MAD(srcType, dst, src0, src1, src2);
- SET_GENIR_DBGINFO(I,1);
}
break;
case Intrinsic::sqrt: this->emitUnaryCallInst(I,CS,ir::OP_SQR); break;
@@ -3857,7 +3815,6 @@ namespace gbe
const ir::Register src1 = this->getRegister(*AI);
const ir::Register dst = this->getRegister(&I);
ctx.POW(ir::TYPE_FLOAT, dst, src0, src1);
- SET_GENIR_DBGINFO(I,1);
break;
}
default: NOT_IMPLEMENTED;
@@ -3884,7 +3841,6 @@ namespace gbe
const ir::Register src = this->getRegister(*AI);
const ir::Register dst = this->getRegister(&I);
ctx.ALU1(ir::OP_ABS, getType(ctx, (*AI)->getType()), dst, src);
- SET_GENIR_DBGINFO(I,1);
break;
}
case GEN_OCL_SIMD_ALL:
@@ -3892,7 +3848,6 @@ namespace gbe
const ir::Register src = this->getRegister(*AI);
const ir::Register dst = this->getRegister(&I);
ctx.ALU1(ir::OP_SIMD_ALL, ir::TYPE_S32, dst, src);
- SET_GENIR_DBGINFO(I,1);
break;
}
case GEN_OCL_SIMD_ANY:
@@ -3900,14 +3855,12 @@ namespace gbe
const ir::Register src = this->getRegister(*AI);
const ir::Register dst = this->getRegister(&I);
ctx.ALU1(ir::OP_SIMD_ANY, ir::TYPE_S32, dst, src);
- SET_GENIR_DBGINFO(I,1);
break;
}
case GEN_OCL_READ_TM:
{
const ir::Register dst = this->getRegister(&I);
ctx.READ_ARF(ir::TYPE_U32, dst, ir::ARF_TM);
- SET_GENIR_DBGINFO(I,1);
break;
}
case GEN_OCL_REGION:
@@ -3922,16 +3875,15 @@ namespace gbe
const ir::Register src = this->getRegister(*AI);
ctx.REGION(dst, src, x.getIntegerValue());
- SET_GENIR_DBGINFO(I,1);
break;
}
case GEN_OCL_RSQ: this->emitUnaryCallInst(I,CS,ir::OP_RSQ); break;
case GEN_OCL_RCP: this->emitUnaryCallInst(I,CS,ir::OP_RCP); break;
case GEN_OCL_FORCE_SIMD8: ctx.setSimdWidth(8); break;
case GEN_OCL_FORCE_SIMD16: ctx.setSimdWidth(16); break;
- case GEN_OCL_LBARRIER: ctx.SYNC(ir::syncLocalBarrier); SET_GENIR_DBGINFO(I,1);break;
- case GEN_OCL_GBARRIER: ctx.SYNC(ir::syncGlobalBarrier); SET_GENIR_DBGINFO(I,1);break;
- case GEN_OCL_LGBARRIER: ctx.SYNC(ir::syncLocalBarrier | ir::syncGlobalBarrier); SET_GENIR_DBGINFO(I,1);break;
+ case GEN_OCL_LBARRIER: ctx.SYNC(ir::syncLocalBarrier); break;
+ case GEN_OCL_GBARRIER: ctx.SYNC(ir::syncGlobalBarrier); break;
+ case GEN_OCL_LGBARRIER: ctx.SYNC(ir::syncLocalBarrier | ir::syncGlobalBarrier); break;
case GEN_OCL_ATOMIC_ADD0:
case GEN_OCL_ATOMIC_ADD1: this->emitAtomicInst(I,CS,ir::ATOMIC_OP_ADD); break;
case GEN_OCL_ATOMIC_SUB0:
@@ -3971,7 +3923,6 @@ namespace gbe
ir::ImageInfoKey key(imageID, infoType);
const ir::Register infoReg = ctx.getFunction().getImageSet()->appendInfo(key, &ctx);
ctx.GET_IMAGE_INFO(infoType, reg, imageID, infoReg);
- SET_GENIR_DBGINFO(I,1);
break;
}
@@ -4024,7 +3975,6 @@ namespace gbe
ctx.SAMPLE(imageID, dstTuple, srcTuple, imageDim, dstType == ir::TYPE_FLOAT,
requiredFloatCoord, sampler, samplerOffset);
- SET_GENIR_DBGINFO(I,1);
break;
}
@@ -4056,7 +4006,6 @@ namespace gbe
}
const ir::Tuple srcTuple = ctx.arrayTuple(&srcTupleData[0], imageDim + 4);
ctx.TYPED_WRITE(imageID, srcTuple, imageDim + 4, srcType, ir::TYPE_U32);
- SET_GENIR_DBGINFO(I,1);
break;
}
case GEN_OCL_MUL_HI_INT:
@@ -4065,7 +4014,6 @@ namespace gbe
GBE_ASSERT(AI != AE); const ir::Register src1 = this->getRegister(*AI); ++AI;
const ir::Register dst = this->getRegister(&I);
ctx.MUL_HI(getType(ctx, I.getType()), dst, src0, src1);
- SET_GENIR_DBGINFO(I,1);
break;
}
case GEN_OCL_MUL_HI_UINT:
@@ -4074,7 +4022,6 @@ namespace gbe
GBE_ASSERT(AI != AE); const ir::Register src1 = this->getRegister(*AI); ++AI;
const ir::Register dst = this->getRegister(&I);
ctx.MUL_HI(getUnsignedType(ctx, I.getType()), dst, src0, src1);
- SET_GENIR_DBGINFO(I,1);
break;
}
case GEN_OCL_MUL_HI_I64:
@@ -4083,7 +4030,6 @@ namespace gbe
GBE_ASSERT(AI != AE); const ir::Register src1 = this->getRegister(*AI); ++AI;
const ir::Register dst = this->getRegister(&I);
ctx.I64_MUL_HI(getType(ctx, I.getType()), dst, src0, src1);
- SET_GENIR_DBGINFO(I,1);
break;
}
case GEN_OCL_MUL_HI_UI64:
@@ -4092,7 +4038,6 @@ namespace gbe
GBE_ASSERT(AI != AE); const ir::Register src1 = this->getRegister(*AI); ++AI;
const ir::Register dst = this->getRegister(&I);
ctx.I64_MUL_HI(getUnsignedType(ctx, I.getType()), dst, src0, src1);
- SET_GENIR_DBGINFO(I,1);
break;
}
case GEN_OCL_UPSAMPLE_SHORT:
@@ -4101,7 +4046,6 @@ namespace gbe
GBE_ASSERT(AI != AE); const ir::Register src1 = this->getRegister(*AI); ++AI;
const ir::Register dst = this->getRegister(&I);
ctx.UPSAMPLE_SHORT(getType(ctx, I.getType()), dst, src0, src1);
- SET_GENIR_DBGINFO(I,1);
break;
}
case GEN_OCL_UPSAMPLE_INT:
@@ -4110,7 +4054,6 @@ namespace gbe
GBE_ASSERT(AI != AE); const ir::Register src1 = this->getRegister(*AI); ++AI;
const ir::Register dst = this->getRegister(&I);
ctx.UPSAMPLE_INT(getType(ctx, I.getType()), dst, src0, src1);
- SET_GENIR_DBGINFO(I,1);
break;
}
case GEN_OCL_UPSAMPLE_LONG:
@@ -4119,7 +4062,6 @@ namespace gbe
GBE_ASSERT(AI != AE); const ir::Register src1 = this->getRegister(*AI); ++AI;
const ir::Register dst = this->getRegister(&I);
ctx.UPSAMPLE_LONG(getType(ctx, I.getType()), dst, src0, src1);
- SET_GENIR_DBGINFO(I,1);
break;
}
case GEN_OCL_SADD_SAT_CHAR:
@@ -4131,7 +4073,6 @@ namespace gbe
GBE_ASSERT(AI != AE); const ir::Register src1 = this->getRegister(*AI); ++AI;
const ir::Register dst = this->getRegister(&I);
ctx.ADDSAT(getType(ctx, I.getType()), dst, src0, src1);
- SET_GENIR_DBGINFO(I,1);
break;
}
case GEN_OCL_UADD_SAT_CHAR:
@@ -4143,7 +4084,6 @@ namespace gbe
GBE_ASSERT(AI != AE); const ir::Register src1 = this->getRegister(*AI); ++AI;
const ir::Register dst = this->getRegister(&I);
ctx.ADDSAT(getUnsignedType(ctx, I.getType()), dst, src0, src1);
- SET_GENIR_DBGINFO(I,1);
break;
}
case GEN_OCL_SSUB_SAT_CHAR:
@@ -4155,7 +4095,6 @@ namespace gbe
GBE_ASSERT(AI != AE); const ir::Register src1 = this->getRegister(*AI); ++AI;
const ir::Register dst = this->getRegister(&I);
ctx.SUBSAT(getType(ctx, I.getType()), dst, src0, src1);
- SET_GENIR_DBGINFO(I,1);
break;
}
case GEN_OCL_USUB_SAT_CHAR:
@@ -4167,7 +4106,6 @@ namespace gbe
GBE_ASSERT(AI != AE); const ir::Register src1 = this->getRegister(*AI); ++AI;
const ir::Register dst = this->getRegister(&I);
ctx.SUBSAT(getUnsignedType(ctx, I.getType()), dst, src0, src1);
- SET_GENIR_DBGINFO(I,1);
break;
}
case GEN_OCL_I64_MAD_SAT:
@@ -4177,7 +4115,6 @@ namespace gbe
GBE_ASSERT(AI != AE); const ir::Register src2 = this->getRegister(*AI); ++AI;
const ir::Register dst = this->getRegister(&I);
ctx.I64MADSAT(getType(ctx, I.getType()), dst, src0, src1, src2);
- SET_GENIR_DBGINFO(I,1);
break;
}
case GEN_OCL_I64_MAD_SATU:
@@ -4187,7 +4124,6 @@ namespace gbe
GBE_ASSERT(AI != AE); const ir::Register src2 = this->getRegister(*AI); ++AI;
const ir::Register dst = this->getRegister(&I);
ctx.I64MADSAT(getUnsignedType(ctx, I.getType()), dst, src0, src1, src2);
- SET_GENIR_DBGINFO(I,1);
break;
}
case GEN_OCL_FMAX:
@@ -4203,9 +4139,7 @@ namespace gbe
ctx.GE(getType(ctx, I.getType()), cmp, src0, src1);
else
ctx.LT(getType(ctx, I.getType()), cmp, src0, src1);
- SET_GENIR_DBGINFO(I,1);
ctx.SEL(getType(ctx, I.getType()), dst, cmp, src0, src1);
- SET_GENIR_DBGINFO(I,1);
break;
}
case GEN_OCL_HADD: {
@@ -4213,7 +4147,6 @@ namespace gbe
GBE_ASSERT(AI != AE); const ir::Register src1 = this->getRegister(*AI); ++AI;
const ir::Register dst = this->getRegister(&I);
ctx.HADD(getUnsignedType(ctx, I.getType()), dst, src0, src1);
- SET_GENIR_DBGINFO(I,1);
break;
}
case GEN_OCL_I64HADD:
@@ -4224,7 +4157,6 @@ namespace gbe
const ir::Register src1 = this->getRegister(*(AI++));
const ir::Register dst = this->getRegister(&I);
ctx.I64HADD(ir::TYPE_U64, dst, src0, src1);
- SET_GENIR_DBGINFO(I,1);
break;
}
case GEN_OCL_RHADD: {
@@ -4232,7 +4164,6 @@ namespace gbe
GBE_ASSERT(AI != AE); const ir::Register src1 = this->getRegister(*AI); ++AI;
const ir::Register dst = this->getRegister(&I);
ctx.RHADD(getUnsignedType(ctx, I.getType()), dst, src0, src1);
- SET_GENIR_DBGINFO(I,1);
break;
}
case GEN_OCL_I64RHADD:
@@ -4243,11 +4174,10 @@ namespace gbe
const ir::Register src1 = this->getRegister(*(AI++));
const ir::Register dst = this->getRegister(&I);
ctx.I64RHADD(ir::TYPE_U64, dst, src0, src1);
- SET_GENIR_DBGINFO(I,1);
break;
}
#define DEF(DST_TYPE, SRC_TYPE) \
- { ctx.SAT_CVT(DST_TYPE, SRC_TYPE, getRegister(&I), getRegister(I.getOperand(0)));SET_GENIR_DBGINFO(I,1); break; }
+ { ctx.SAT_CVT(DST_TYPE, SRC_TYPE, getRegister(&I), getRegister(I.getOperand(0))); break; }
case GEN_OCL_SAT_CONV_U8_TO_I8:
DEF(ir::TYPE_S8, ir::TYPE_U8);
case GEN_OCL_SAT_CONV_I16_TO_I8:
@@ -4310,11 +4240,9 @@ namespace gbe
DEF(ir::TYPE_U32, ir::TYPE_HALF);
case GEN_OCL_CONV_F16_TO_F32:
ctx.F16TO32(ir::TYPE_FLOAT, ir::TYPE_U16, getRegister(&I), getRegister(I.getOperand(0)));
- SET_GENIR_DBGINFO(I,1);
break;
case GEN_OCL_CONV_F32_TO_F16:
ctx.F32TO16(ir::TYPE_U16, ir::TYPE_FLOAT, getRegister(&I), getRegister(I.getOperand(0)));
- SET_GENIR_DBGINFO(I,1);
break;
#undef DEF
@@ -4329,14 +4257,12 @@ namespace gbe
{
const ir::Register dst = this->getRegister(&I);
ctx.ALU0(ir::OP_SIMD_SIZE, getType(ctx, I.getType()), dst);
- SET_GENIR_DBGINFO(I,1);
break;
}
case GEN_OCL_SIMD_ID:
{
const ir::Register dst = this->getRegister(&I);
ctx.ALU0(ir::OP_SIMD_ID, getType(ctx, I.getType()), dst);
- SET_GENIR_DBGINFO(I,1);
break;
}
case GEN_OCL_SIMD_SHUFFLE:
@@ -4345,7 +4271,6 @@ namespace gbe
const ir::Register src1 = this->getRegister(*AI); ++AI;
const ir::Register dst = this->getRegister(&I);
ctx.SIMD_SHUFFLE(getType(ctx, I.getType()), dst, src0, src1);
- SET_GENIR_DBGINFO(I,1);
break;
}
default: break;
@@ -4392,6 +4317,7 @@ namespace gbe
// below code assume align is power of 2
GBE_ASSERT(align && (align & (align-1)) == 0);
+ SET_GENIR_DBGINFO(I,1);
// align the stack pointer according to data alignment
if(align > 1) {
uint32_t prevStackPtr = ctx.getFunction().getStackSize();
@@ -4400,20 +4326,15 @@ namespace gbe
ir::ImmediateIndex stepImm = ctx.newIntegerImmediate(step, ir::TYPE_U32);
ir::Register stepReg = ctx.reg(ctx.getPointerFamily());
ctx.LOADI(ir::TYPE_U32, stepReg, stepImm);
- SET_GENIR_DBGINFO(I,1);
ctx.ADD(ir::TYPE_U32, stack, stack, stepReg);
- SET_GENIR_DBGINFO(I,1);
ctx.getFunction().pushStackSize(step);
}
}
// Set the destination register properly
ctx.MOV(imm.getType(), dst, stack);
- SET_GENIR_DBGINFO(I,1);
ctx.LOADI(imm.getType(), reg, immIndex);
- SET_GENIR_DBGINFO(I,1);
ctx.ADD(imm.getType(), stack, stack, reg);
- SET_GENIR_DBGINFO(I,1);
ctx.getFunction().pushStackSize(elementSize);
}
@@ -4438,6 +4359,7 @@ namespace gbe
uint32_t msgNum = totalSize > 16 ? totalSize / 16 : 1;
const uint32_t perMsgNum = elemNum / msgNum;
+ SET_GENIR_DBGINFO(llvmValues,3);
for (uint32_t msg = 0; msg < msgNum; ++msg) {
// Build the tuple data in the vector
vector<ir::Register> tupleData; // put registers here
@@ -4473,9 +4395,7 @@ namespace gbe
addr = ctx.reg(pointerFamily);
ctx.LOADI(immType, offset, immIndex);
- SET_GENIR_DBGINFO(llvmValues,3);
ctx.ADD(immType, addr, ptr, offset);
- SET_GENIR_DBGINFO(llvmValues,3);
}
// Emit the instruction
@@ -4483,7 +4403,6 @@ namespace gbe
ctx.LOAD(type, tuple, addr, addrSpace, perMsgNum, dwAligned, fixedBTI, bti);
else
ctx.STORE(type, tuple, addr, addrSpace, perMsgNum, dwAligned, fixedBTI, bti);
- SET_GENIR_DBGINFO(llvmValues,3);
}
}
@@ -4521,14 +4440,12 @@ namespace gbe
}
const ir::Tuple byteTuple = ctx.arrayTuple(&byteTupleData[0], byteSize);
+ SET_GENIR_DBGINFO(llvmValues,3);
if (isLoad) {
ctx.LOAD(ir::TYPE_U8, byteTuple, ptr, addrSpace, byteSize, dwAligned, fixedBTI, bti);
- SET_GENIR_DBGINFO(llvmValues,3);
ctx.BITCAST(type, ir::TYPE_U8, tuple, byteTuple, elemNum, byteSize);
- SET_GENIR_DBGINFO(llvmValues,3);
} else {
ctx.BITCAST(ir::TYPE_U8, type, byteTuple, tuple, byteSize, elemNum);
- SET_GENIR_DBGINFO(llvmValues,3);
// FIXME: byte scatter does not handle correctly vector store, after fix that,
// we can directly use on store instruction like:
// ctx.STORE(ir::TYPE_U8, byteTuple, ptr, addrSpace, byteSize, dwAligned, fixedBTI, bti);
@@ -4544,12 +4461,9 @@ namespace gbe
immIndex = ctx.newImmediate(int32_t(elemID));
addr = ctx.reg(pointerFamily);
ctx.LOADI(ir::TYPE_S32, offset, immIndex);
- SET_GENIR_DBGINFO(llvmValues,3);
ctx.ADD(ir::TYPE_S32, addr, ptr, offset);
- SET_GENIR_DBGINFO(llvmValues,3);
}
ctx.STORE(type, addr, addrSpace, dwAligned, fixedBTI, bti, reg);
- SET_GENIR_DBGINFO(llvmValues,3);
}
}
}
@@ -4576,6 +4490,7 @@ namespace gbe
ir::Register btiReg;
bool fixedBTI = false;
+ SET_GENIR_DBGINFO(I,1);
if (isa<ConstantInt>(bti)) {
fixedBTI = true;
unsigned index = cast<ConstantInt>(bti)->getZExtValue();
@@ -4583,7 +4498,6 @@ namespace gbe
ir::ImmediateIndex immIndex = ctx.newImmediate((uint32_t)index);
btiReg = ctx.reg(ir::FAMILY_DWORD);
ctx.LOADI(ir::TYPE_U32, btiReg, immIndex);
- SET_GENIR_DBGINFO(I,1);
} else {
addrSpace = ir::MEM_MIXED;
btiReg = this->getRegister(bti);
@@ -4601,7 +4515,6 @@ namespace gbe
// so, I avoid subtracting zero base to satisfy ArgumentLower pass.
if (!zeroBase) {
ctx.SUB(ir::TYPE_U32, ptr, pointer, baseReg);
- SET_GENIR_DBGINFO(I,1);
}
else
ptr = pointer;
@@ -4621,7 +4534,6 @@ namespace gbe
ctx.LOAD(type, ptr, addrSpace, dwAligned, fixedBTI, btiReg, values);
else
ctx.STORE(type, ptr, addrSpace, dwAligned, fixedBTI, btiReg, values);
- SET_GENIR_DBGINFO(I,1);
}
// A vector type requires to build a tuple
else {
@@ -4667,7 +4579,6 @@ namespace gbe
ctx.LOAD(type, tuple, ptr, addrSpace, elemNum, dwAligned, fixedBTI, btiReg);
else
ctx.STORE(type, tuple, ptr, addrSpace, elemNum, dwAligned, fixedBTI, btiReg);
- SET_GENIR_DBGINFO(I,1);
}
// Not supported by the hardware. So, we split the message and we use
// strided loads and stores
@@ -4694,15 +4605,12 @@ namespace gbe
immIndex = ctx.newImmediate(int32_t(elemID * elemSize));
addr = ctx.reg(pointerFamily);
ctx.LOADI(ir::TYPE_S32, offset, immIndex);
- SET_GENIR_DBGINFO(I,1);
ctx.ADD(ir::TYPE_S32, addr, ptr, offset);
- SET_GENIR_DBGINFO(I,1);
}
if (isLoad)
ctx.LOAD(type, addr, addrSpace, dwAligned, fixedBTI, btiReg, reg);
else
ctx.STORE(type, addr, addrSpace, dwAligned, fixedBTI, btiReg, reg);
- SET_GENIR_DBGINFO(I,1);
}
}
}
diff --git a/backend/src/llvm/llvm_to_gen.cpp b/backend/src/llvm/llvm_to_gen.cpp
index 012b754..19e681f 100644
--- a/backend/src/llvm/llvm_to_gen.cpp
+++ b/backend/src/llvm/llvm_to_gen.cpp
@@ -303,10 +303,10 @@ namespace gbe
passes.add(createScalarizePass()); // Expand all vector ops
//setenv("OCL_PROFILING","0",0);
- if(OCL_PROFILING) {
+ /*if(OCL_PROFILING) {
passes.add(createTimestampParserPass()); // by ynbai
passes.add(createExpandConstantExprPass());
- }
+ }*/
if(OCL_OUTPUT_CFG)
passes.add(createCFGPrinterPass());
--
1.9.1
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