[Beignet] [PATCH V2 07/17] Backend: Fix workgroup op masked elements by proper init value
Grigore Lupescu
grigore.lupescu at intel.com
Mon Apr 11 14:37:25 UTC 2016
From: Grigore Lupescu <grigore.lupescu at intel.com>
Signed-off-by: Grigore Lupescu <grigore.lupescu at intel.com>
---
backend/src/backend/gen_context.cpp | 17 +++++++++++++----
1 file changed, 13 insertions(+), 4 deletions(-)
diff --git a/backend/src/backend/gen_context.cpp b/backend/src/backend/gen_context.cpp
index cac78a9..38bd0f2 100644
--- a/backend/src/backend/gen_context.cpp
+++ b/backend/src/backend/gen_context.cpp
@@ -2395,8 +2395,7 @@ namespace gbe
if (wg_op == ir::WORKGROUP_OP_ALL)
{
if (dataReg.type == GEN_TYPE_D
- || dataReg.type == GEN_TYPE_UD
- || dataReg.type == GEN_TYPE_F)
+ || dataReg.type == GEN_TYPE_UD)
p->MOV(dataReg, GenRegister::immd(0xFFFFFFFF));
else if(dataReg.type == GEN_TYPE_L ||
dataReg.type == GEN_TYPE_UL)
@@ -2619,8 +2618,8 @@ namespace gbe
*/
void GenContext::emitWorkGroupOpInstruction(const SelectionInstruction &insn){
const GenRegister dst = ra->genReg(insn.dst(0));
- const GenRegister tmp = ra->genReg(insn.dst(1));
- const GenRegister theVal = ra->genReg(insn.src(2));
+ const GenRegister tmp = GenRegister::retype(ra->genReg(insn.dst(1)), dst.type);
+ const GenRegister theVal = GenRegister::retype(ra->genReg(insn.src(2)), dst.type);
GenRegister threadData = ra->genReg(insn.src(3));
GenRegister partialData = GenRegister::toUniform(threadData, dst.type);
GenRegister threadId = ra->genReg(insn.src(0));
@@ -2631,6 +2630,16 @@ namespace gbe
uint32_t simd = p->curr.execWidth;
int32_t jip0, jip1;
+ /* Masked elements should be properly set to init value */
+ p->push(); {
+ p->curr.noMask = 1;
+ initValue(p, tmp, wg_op);
+ p->curr.noMask = 0;
+ p->MOV(tmp, theVal);
+ p->curr.noMask = 1;
+ p->MOV(theVal, tmp);
+ } p->pop();
+
threadId = GenRegister::toUniform(threadId, GEN_TYPE_UD);
/* Use of continuous GRF allocation from insn selection */
--
2.5.0
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