[Beignet] [PATCH OCL20 V2] GBE: imm64 should not be in src1 per hardware spec. V2: Refine assert to check if the value of imm can not be a imm32

[Xiuli Pan]

From: Ruiling Song <ruiling.song at intel.com>

Signed-off-by: Ruiling Song <ruiling.song at intel.com>
Contributor: Pan Xiuli <xiuli.pan at intel.com>
---
 backend/src/backend/gen8_encoder.cpp       |  5 +++--
 backend/src/backend/gen_insn_selection.cpp | 12 ++++++++----
 2 files changed, 11 insertions(+), 6 deletions(-)

diff --git a/backend/src/backend/gen8_encoder.cpp b/backend/src/backend/gen8_encoder.cpp
index 55b9f05..632e542 100644
--- a/backend/src/backend/gen8_encoder.cpp
+++ b/backend/src/backend/gen8_encoder.cpp
@@ -649,9 +649,10 @@ namespace gbe
 
     assert(gen8_insn->bits1.da1.src0_reg_file != GEN_IMMEDIATE_VALUE);
 
-    if (reg.file == GEN_IMMEDIATE_VALUE)
+    if (reg.file == GEN_IMMEDIATE_VALUE) {
+      assert(!((reg.type == GEN_TYPE_L || reg.type == GEN_TYPE_UL || reg.type == GEN_TYPE_DF_IMM) && reg.value.u64 > 0xFFFFFFFFl));
       gen8_insn->bits3.ud = reg.value.ud;
-    else {
+    } else {
       assert (reg.address_mode == GEN_ADDRESS_DIRECT);
       if (gen8_insn->header.access_mode == GEN_ALIGN_1) {
         gen8_insn->bits3.da1.src1_subreg_nr = reg.subnr;
diff --git a/backend/src/backend/gen_insn_selection.cpp b/backend/src/backend/gen_insn_selection.cpp
index f3624ba..f5b104b 100644
--- a/backend/src/backend/gen_insn_selection.cpp
+++ b/backend/src/backend/gen_insn_selection.cpp
@@ -3980,8 +3980,10 @@ namespace gbe
           }
           if (addrFamily == FAMILY_DWORD)
             sel.AND(tmpAddr, GenRegister::retype(address,GEN_TYPE_UD), GenRegister::immud(0xfffffffc));
-          else
-            sel.AND(tmpAddr, GenRegister::retype(address,GEN_TYPE_UL), GenRegister::immuint64(0xfffffffffffffffc));
+          else {
+            sel.MOV(tmpAddr, GenRegister::immuint64(0xfffffffffffffffc));
+            sel.AND(tmpAddr, GenRegister::retype(address,GEN_TYPE_UL), tmpAddr);
+          }
 
         sel.pop();
         sel.push();
@@ -4213,8 +4215,10 @@ namespace gbe
             sel.curr.noMask = 1;
           if (addrFamily == FAMILY_DWORD)
             sel.AND(alignedAddr, GenRegister::retype(address, GEN_TYPE_UD), GenRegister::immud(~0x3));
-          else
-            sel.AND(alignedAddr, GenRegister::retype(address, GEN_TYPE_UL), GenRegister::immuint64(~0x3ul));
+          else {
+            sel.MOV(alignedAddr,  GenRegister::immuint64(~0x3ul));
+            sel.AND(alignedAddr, GenRegister::retype(address, GEN_TYPE_UL), alignedAddr);
+          }
         sel.pop();
 
         uint32_t remainedReg = effectDataNum + 1;
-- 
2.5.0