[Beignet] [PATCH 3/5] GBE: imm64 should not be in src1 per hardware spec.

[Pan, Xiuli]

The patch set LGTM!
I have sent a V2 for this patch, since we should check if the immediate value is 64 bit.

-----Original Message-----
From: Beignet [mailto:beignet-bounces at lists.freedesktop.org] On Behalf Of Ruiling Song
Sent: Thursday, April 7, 2016 2:40 PM
To: beignet at lists.freedesktop.org
Cc: Song, Ruiling <ruiling.song at intel.com>
Subject: [Beignet] [PATCH 3/5] GBE: imm64 should not be in src1 per hardware spec.

Signed-off-by: Ruiling Song <ruiling.song at intel.com>
---
 backend/src/backend/gen8_encoder.cpp       |  5 +++--
 backend/src/backend/gen_insn_selection.cpp | 12 ++++++++----
 2 files changed, 11 insertions(+), 6 deletions(-)

diff --git a/backend/src/backend/gen8_encoder.cpp b/backend/src/backend/gen8_encoder.cpp
index a71e44a..7592f76 100644
--- a/backend/src/backend/gen8_encoder.cpp
+++ b/backend/src/backend/gen8_encoder.cpp
@@ -649,9 +649,10 @@ namespace gbe
 
     assert(gen8_insn->bits1.da1.src0_reg_file != GEN_IMMEDIATE_VALUE);
 
-    if (reg.file == GEN_IMMEDIATE_VALUE)
+    if (reg.file == GEN_IMMEDIATE_VALUE) {
+      assert(reg.type != GEN_TYPE_L && reg.type != GEN_TYPE_UL && 
+ reg.type != GEN_TYPE_DF_IMM);
       gen8_insn->bits3.ud = reg.value.ud;
-    else {
+    } else {
       assert (reg.address_mode == GEN_ADDRESS_DIRECT);
       if (gen8_insn->header.access_mode == GEN_ALIGN_1) {
         gen8_insn->bits3.da1.src1_subreg_nr = reg.subnr; diff --git a/backend/src/backend/gen_insn_selection.cpp b/backend/src/backend/gen_insn_selection.cpp
index 77614b6..7a58d4a 100644
--- a/backend/src/backend/gen_insn_selection.cpp
+++ b/backend/src/backend/gen_insn_selection.cpp
@@ -3953,8 +3953,10 @@ namespace gbe
           }
           if (addrFamily == FAMILY_DWORD)
             sel.AND(tmpAddr, GenRegister::retype(address,GEN_TYPE_UD), GenRegister::immud(0xfffffffc));
-          else
-            sel.AND(tmpAddr, GenRegister::retype(address,GEN_TYPE_UL), GenRegister::immuint64(0xfffffffffffffffc));
+          else {
+            sel.MOV(tmpAddr, GenRegister::immuint64(0xfffffffffffffffc));
+            sel.AND(tmpAddr, GenRegister::retype(address,GEN_TYPE_UL), tmpAddr);
+          }
 
         sel.pop();
         sel.push();
@@ -4186,8 +4188,10 @@ namespace gbe
             sel.curr.noMask = 1;
           if (addrFamily == FAMILY_DWORD)
             sel.AND(alignedAddr, GenRegister::retype(address, GEN_TYPE_UD), GenRegister::immud(~0x3));
-          else
-            sel.AND(alignedAddr, GenRegister::retype(address, GEN_TYPE_UL), GenRegister::immuint64(~0x3ul));
+          else {
+            sel.MOV(alignedAddr,  GenRegister::immuint64(~0x3ul));
+            sel.AND(alignedAddr, GenRegister::retype(address, GEN_TYPE_UL), alignedAddr);
+          }
         sel.pop();
 
         uint32_t remainedReg = effectDataNum + 1;
--
2.4.1

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