[Beignet] [PATCH V2 2/2] write mask in disassembly not parse correctly.

[xionghu.luo at intel.com]

From: Luo Xionghu <xionghu.luo at intel.com>

v2: don't show write mask when full channel; split patch.

Signed-off-by: Luo Xionghu <xionghu.luo at intel.com>
---
 backend/src/backend/gen/gen_mesa_disasm.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/backend/src/backend/gen/gen_mesa_disasm.c b/backend/src/backend/gen/gen_mesa_disasm.c
index 26393f4..067ddd8 100644
--- a/backend/src/backend/gen/gen_mesa_disasm.c
+++ b/backend/src/backend/gen/gen_mesa_disasm.c
@@ -781,7 +781,7 @@ static int dest_3src(FILE *file, const void *inst)
   if (is_special_acc(inst)) {
     err |= control(file, "specialacc", special_acc, ((const union Gen8NativeInstruction *)inst)->bits1.da3srcacc.dst_special_acc, NULL);
   } else {
-    err |= control(file, "writemask", writemask, GEN_BITS_FIELD(inst, bits1.da16.dest_writemask), NULL);
+    err |= control(file, "writemask", writemask, GEN_BITS_FIELD(inst, bits1.da3src.dest_writemask), NULL);
   }
 
   if (gen_version < 80) {
-- 
2.1.4