[Beignet] [PATCH 2/7] Backend: Refine flag usage in instrction selection
Yang, Rong R
rong.r.yang at intel.com
Fri Dec 9 06:58:24 UTC 2016
Pushed the first 5 of 7 of this patchset.
As discuss offline, remove some useless "sel.curr.flag = 0; sel.curr.subFlag = 1;" code when sel.curr.physicalFlag = 0;
> -----Original Message-----
> From: Beignet [mailto:beignet-bounces at lists.freedesktop.org] On Behalf Of
> Xiuli Pan
> Sent: Monday, November 14, 2016 16:20
> To: beignet at lists.freedesktop.org
> Cc: Pan, Xiuli <xiuli.pan at intel.com>
> Subject: [Beignet] [PATCH 2/7] Backend: Refine flag usage in instrction
> selection
>
> From: Pan Xiuli <xiuli.pan at intel.com>
>
> We used to mix use physical and virtuial flags in instrction selection and it will
> confuse the denpendency track in instrction scheduling.
> Refine all physical flag in instrction selection stage to flag 0.1 and remove the
> flag 0.0 reserve.
>
> Signed-off-by: Pan Xiuli <xiuli.pan at intel.com>
> ---
> backend/src/backend/gen_insn_selection.cpp | 35
> +++++++++++++++++++++++++-----
> backend/src/backend/gen_insn_selection.hpp | 1 -
> backend/src/backend/gen_reg_allocation.cpp | 10 ++-------
> 3 files changed, 31 insertions(+), 15 deletions(-)
>
> diff --git a/backend/src/backend/gen_insn_selection.cpp
> b/backend/src/backend/gen_insn_selection.cpp
> index c14e0bc..5adcaed 100644
> --- a/backend/src/backend/gen_insn_selection.cpp
> +++ b/backend/src/backend/gen_insn_selection.cpp
> @@ -246,7 +246,7 @@ namespace gbe
> // SelectionBlock
> ///////////////////////////////////////////////////////////////////////////
>
> - SelectionBlock::SelectionBlock(const ir::BasicBlock *bb) : bb(bb),
> isLargeBlock(false), endifLabel( (ir::LabelIndex) 0),
> removeSimpleIfEndif(false){}
> + SelectionBlock::SelectionBlock(const ir::BasicBlock *bb) : bb(bb),
> + endifLabel( (ir::LabelIndex) 0), removeSimpleIfEndif(false){}
>
> void SelectionBlock::append(ir::Register reg) { tmp.push_back(reg); }
>
> @@ -1118,7 +1118,7 @@ namespace gbe
> if(this->block->removeSimpleIfEndif){
> mov->state.predicate = GEN_PREDICATE_NORMAL;
> mov->state.flag = 0;
> - mov->state.subFlag = 0;
> + mov->state.subFlag = 1;
> }
> if (this->isScalarReg(insn->src(regID).reg()))
> mov->state.noMask = 1;
> @@ -1152,7 +1152,7 @@ namespace gbe
> if(this->block->removeSimpleIfEndif){
> mov->state.predicate = GEN_PREDICATE_NORMAL;
> mov->state.flag = 0;
> - mov->state.subFlag = 0;
> + mov->state.subFlag = 1;
> }
> if (simdWidth == 1) {
> mov->state.noMask = 1;
> @@ -2562,7 +2562,7 @@ extern bool OCL_DEBUGINFO; // first defined by
> calling BVAR in program.cpp
> this->push();
> this->curr.predicate = GEN_PREDICATE_NORMAL;
> this->curr.flag = 0;
> - this->curr.subFlag = 0;
> + this->curr.subFlag = 1;
> }
> // If there is no branch at the end of this block.
>
> @@ -2577,7 +2577,7 @@ extern bool OCL_DEBUGINFO; // first defined by
> calling BVAR in program.cpp
> if(this->block->removeSimpleIfEndif){
> this->curr.predicate = GEN_PREDICATE_NONE;
> this->curr.flag = 0;
> - this->curr.subFlag = 0;
> + this->curr.subFlag = 1;
> this->pop();
> }
> // If we are in if/endif fix mode, and this block is @@ -2587,13 +2587,14
> @@ extern bool OCL_DEBUGINFO; // first defined by calling BVAR in
> program.cpp
> this->block->insnList.size() != 0 &&
> this->block->insnList.size() % 1000 == 0 &&
> this->block->endifLabel.value() != 0) {
> + this->curr.flag = 0;
> + this->curr.subFlag = 1;
> ir::LabelIndex jip = this->block->endifLabel;
> this->ENDIF(GenRegister::immd(0), jip);
> this->push();
> this->curr.predicate = GEN_PREDICATE_NORMAL;
> this->IF(GenRegister::immd(0), jip, jip);
> this->pop();
> - this->block->isLargeBlock = true;
> }
> // Output the code in the current basic block
> this->endBackwardGeneration();
> @@ -6534,6 +6535,8 @@ extern bool OCL_DEBUGINFO; // first defined by
> calling BVAR in program.cpp
> sel.push();
> sel.curr.noMask = 1;
> sel.curr.predicate = GEN_PREDICATE_NONE;
> + sel.curr.flag = 0;
> + sel.curr.subFlag = 1;
> sel.cmpBlockIP(GEN_CONDITIONAL_LE, src0, src1);
> sel.pop();
>
> @@ -6544,6 +6547,8 @@ extern bool OCL_DEBUGINFO; // first defined by
> calling BVAR in program.cpp
> // this block, as it will always excute with all lanes activated.
> sel.push();
> sel.curr.predicate = GEN_PREDICATE_NORMAL;
> + sel.curr.flag = 0;
> + sel.curr.subFlag = 1;
> sel.setBlockIP(src0, sel.ctx.getMaxLabel());
> sel.curr.predicate = GEN_PREDICATE_NONE;
> sel.curr.noMask = 1;
> @@ -6562,6 +6567,8 @@ extern bool OCL_DEBUGINFO; // first defined by
> calling BVAR in program.cpp
> // FIXME, if the last BRA is unconditional jump, we don't need to update
> the label here.
> sel.push();
> sel.curr.predicate = GEN_PREDICATE_NORMAL;
> + sel.curr.flag = 0;
> + sel.curr.subFlag = 1;
> sel.setBlockIP(src0, label.value());
> sel.pop();
> }
> @@ -6573,6 +6580,8 @@ extern bool OCL_DEBUGINFO; // first defined by
> calling BVAR in program.cpp
> (jip != nextLabel || sel.block->endifOffset != -1)) {
> // If it is required, insert a JUMP to bypass the block
> sel.push();
> + sel.curr.flag = 0;
> + sel.curr.subFlag = 1;
> if (simdWidth == 8)
> sel.curr.predicate = GEN_PREDICATE_ALIGN1_ANY8H;
> else if (simdWidth == 16)
> @@ -6587,6 +6596,8 @@ extern bool OCL_DEBUGINFO; // first defined by
> calling BVAR in program.cpp
> }
> if(!sel.block->removeSimpleIfEndif){
> sel.push();
> + sel.curr.flag = 0;
> + sel.curr.subFlag = 1;
> sel.curr.predicate = GEN_PREDICATE_NORMAL;
> if(!insn.getParent()->needEndif && insn.getParent()->needIf) {
> ir::LabelIndex label = insn.getParent()->endifLabel; @@ -7143,6
> +7154,8 @@ extern bool OCL_DEBUGINFO; // first defined by calling BVAR in
> program.cpp
> sel.curr.physicalFlag = 0;
> sel.curr.flagIndex = pred.value();
> sel.curr.predicate = GEN_PREDICATE_NORMAL;
> + sel.curr.flag = 0;
> + sel.curr.subFlag = 1;
> sel.setBlockIP(ip, dst.value());
> sel.curr.predicate = GEN_PREDICATE_NONE;
> if (!sel.block->hasBarrier && !sel.block->removeSimpleIfEndif) @@ -
> 7152,6 +7165,8 @@ extern bool OCL_DEBUGINFO; // first defined by calling
> BVAR in program.cpp
> } else {
> // Update the PcIPs
> const LabelIndex jip = sel.ctx.getLabelIndex(&insn);
> + sel.curr.flag = 0;
> + sel.curr.subFlag = 1;
> if(insn.getParent()->needEndif)
> sel.setBlockIP(ip, dst.value());
>
> @@ -7202,6 +7217,8 @@ extern bool OCL_DEBUGINFO; // first defined by
> calling BVAR in program.cpp
> sel.curr.physicalFlag = 0;
> sel.curr.flagIndex = pred.value();
> sel.curr.predicate = GEN_PREDICATE_NORMAL;
> + sel.curr.flag = 0;
> + sel.curr.subFlag = 1;
> sel.setBlockIP(ip, dst.value());
> sel.block->endifOffset = -1;
> sel.curr.predicate = GEN_PREDICATE_NONE; @@ -7218,6 +7235,8 @@
> extern bool OCL_DEBUGINFO; // first defined by calling BVAR in program.cpp
> } else {
> const LabelIndex next = bb.getNextBlock()->getLabelIndex();
> // Update the PcIPs
> + sel.curr.flag = 0;
> + sel.curr.subFlag = 1;
> if(insn.getParent()->needEndif)
> sel.setBlockIP(ip, dst.value());
> sel.block->endifOffset = -1;
> @@ -7274,6 +7293,8 @@ extern bool OCL_DEBUGINFO; // first defined by
> calling BVAR in program.cpp
> sel.curr.externFlag = 1;
> sel.curr.inversePredicate = insn.getInversePredicated();
> sel.curr.predicate = GEN_PREDICATE_NORMAL;
> + sel.curr.flag = 0;
> + sel.curr.subFlag = 1;
> sel.IF(GenRegister::immd(0), jip, uip);
> sel.curr.inversePredicate = 0;
> sel.pop();
> @@ -7296,6 +7317,8 @@ extern bool OCL_DEBUGINFO; // first defined by
> calling BVAR in program.cpp
> sel.curr.externFlag = 1;
> sel.curr.inversePredicate = insn.getInversePredicated();
> sel.curr.predicate = GEN_PREDICATE_NORMAL;
> + sel.curr.flag = 0;
> + sel.curr.subFlag = 1;
> sel.WHILE(GenRegister::immd(0), jip);
> sel.curr.inversePredicate = 0;
> sel.pop();
> diff --git a/backend/src/backend/gen_insn_selection.hpp
> b/backend/src/backend/gen_insn_selection.hpp
> index 14ac05f..ba287e8 100644
> --- a/backend/src/backend/gen_insn_selection.hpp
> +++ b/backend/src/backend/gen_insn_selection.hpp
> @@ -253,7 +253,6 @@ namespace gbe
> void append(SelectionInstruction *insn);
> /*! Append a new selection instruction at the beginning of the block */
> void prepend(SelectionInstruction *insn);
> - bool isLargeBlock;
> ir::LabelIndex endifLabel;
> int endifOffset;
> bool hasBarrier;
> diff --git a/backend/src/backend/gen_reg_allocation.cpp
> b/backend/src/backend/gen_reg_allocation.cpp
> index 5b25d1b..2a889a0 100644
> --- a/backend/src/backend/gen_reg_allocation.cpp
> +++ b/backend/src/backend/gen_reg_allocation.cpp
> @@ -148,7 +148,6 @@ namespace gbe
> vector<GenRegInterval> intervals;
> /*! All the boolean register intervals on the corresponding BB*/
> typedef map<ir::Register, GenRegInterval> RegIntervalMap;
> - set<SelectionBlock *> flag0ReservedBlocks;
> map<SelectionBlock *, RegIntervalMap *> boolIntervalsMap;
> /*! Intervals sorting based on starting point positions */
> vector<GenRegInterval*> starting;
> @@ -503,7 +502,7 @@ namespace gbe
> map<ir::Register, uint32_t> allocatedFlags;
> map<const GenRegInterval*, uint32_t> allocatedFlagIntervals;
>
> - const uint32_t flagNum = flag0ReservedBlocks.contains(&block) ? 2 : 3;
> + const uint32_t flagNum = 3;
> uint32_t freeFlags[] = {2, 3, 0};
> uint32_t freeNum = flagNum;
> if (boolIntervalsMap.find(&block) == boolIntervalsMap.end()) @@ -
> 1235,8 +1234,6 @@ namespace gbe
> // Update the intervals of each used register. Note that we do not
> // register allocate R0, so we skip all sub-registers in r0
> RegIntervalMap *boolsMap = new RegIntervalMap;
> - if (block.isLargeBlock)
> - flag0ReservedBlocks.insert(&block);
> for (auto &insn : block.insnList) {
> const uint32_t srcNum = insn.srcNum, dstNum = insn.dstNum;
> insn.ID = insnID;
> @@ -1309,8 +1306,6 @@ namespace gbe
> // is out-of the if/endif region, so we have to borrow the f0
> // to get correct bits for all channels.
> boolsMap->find(reg)->second.minID = 0;
> - if (flag0ReservedBlocks.contains(&block))
> - flag0ReservedBlocks.erase(&block);
> }
> } else {
> // Make sure that instruction selection stage didn't use physiacl flags
> incorrectly.
> @@ -1319,8 +1314,7 @@ namespace gbe
> insn.opcode == SEL_OP_JMPI ||
> insn.state.predicate == GEN_PREDICATE_NONE ||
> (block.hasBarrier && insn.opcode == SEL_OP_MOV) ||
> - (insn.state.flag == 0 && insn.state.subFlag == 1) ||
> - (block.removeSimpleIfEndif && insn.state.flag == 0 &&
> insn.state.subFlag == 0) ));
> + (insn.state.flag == 0 && insn.state.subFlag ==
> + 1) ));
> }
> lastID = insnID;
> insnID++;
> --
> 2.7.4
>
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