[Beignet] [PATCH 5/5] enable sends for typed write
Guo, Yejun
yejun.guo at intel.com
Fri Dec 9 10:10:40 UTC 2016
Signed-off-by: Guo, Yejun <yejun.guo at intel.com>
---
backend/src/backend/gen9_encoder.cpp | 22 +++++++++++++++++++++
backend/src/backend/gen9_encoder.hpp | 1 +
backend/src/backend/gen_context.cpp | 3 ++-
backend/src/backend/gen_encoder.cpp | 2 +-
backend/src/backend/gen_encoder.hpp | 4 +++-
backend/src/backend/gen_insn_selection.cpp | 31 ++++++++++++++++++++++++------
backend/src/backend/gen_insn_selection.hpp | 1 +
7 files changed, 55 insertions(+), 9 deletions(-)
diff --git a/backend/src/backend/gen9_encoder.cpp b/backend/src/backend/gen9_encoder.cpp
index b42c833..cfbf985 100644
--- a/backend/src/backend/gen9_encoder.cpp
+++ b/backend/src/backend/gen9_encoder.cpp
@@ -146,6 +146,28 @@ namespace gbe
}
}
+ void Gen9Encoder::TYPED_WRITE(GenRegister header, GenRegister data, bool header_present, unsigned char bti, bool useSends)
+ {
+ if (!useSends)
+ Gen8Encoder::TYPED_WRITE(header, data, header_present, bti, false);
+ else {
+ assert(header.reg() != data.reg());
+
+ GenNativeInstruction *insn = this->next(GEN_OPCODE_SENDS);
+ Gen9NativeInstruction *gen9_insn = &insn->gen9_insn;
+ assert(header_present);
+
+ this->setHeader(insn);
+ insn->header.destreg_or_condmod = GEN_SFID_DATAPORT1_DATA;
+
+ setSendsOperands(gen9_insn, GenRegister::null(), header, data);
+ gen9_insn->bits2.sends.src1_length = 4; //src0_length: 5(header+u+v+w+lod), src1_length: 4(data)
+
+ gen9_insn->bits2.sends.sel_reg32_desc = 0;
+ setTypedWriteMessage(insn, bti, GEN_TYPED_WRITE, 5, header_present);
+ }
+ }
+
unsigned Gen9Encoder::setByteScatterSendsMessageDesc(GenNativeInstruction *insn, unsigned bti, unsigned elemSize)
{
uint32_t msg_length = 0;
diff --git a/backend/src/backend/gen9_encoder.hpp b/backend/src/backend/gen9_encoder.hpp
index 9b3af13..d754d59 100644
--- a/backend/src/backend/gen9_encoder.hpp
+++ b/backend/src/backend/gen9_encoder.hpp
@@ -49,6 +49,7 @@ namespace gbe
bool isUniform);
void setSendsOperands(Gen9NativeInstruction *gen9_insn, GenRegister dst, GenRegister src0, GenRegister src1);
virtual void UNTYPED_WRITE(GenRegister addr, GenRegister data, GenRegister bti, uint32_t elemNum, bool useSends);
+ virtual void TYPED_WRITE(GenRegister header, GenRegister data, bool header_present, unsigned char bti, bool useSends);
virtual unsigned setUntypedWriteSendsMessageDesc(GenNativeInstruction *insn, unsigned bti, unsigned elemNum);
virtual void BYTE_SCATTER(GenRegister addr, GenRegister data, GenRegister bti, uint32_t elemSize, bool useSends);
virtual unsigned setByteScatterSendsMessageDesc(GenNativeInstruction *insn, unsigned bti, unsigned elemSize);
diff --git a/backend/src/backend/gen_context.cpp b/backend/src/backend/gen_context.cpp
index d161ebf..c8019e3 100644
--- a/backend/src/backend/gen_context.cpp
+++ b/backend/src/backend/gen_context.cpp
@@ -2465,8 +2465,9 @@ namespace gbe
void GenContext::emitTypedWriteInstruction(const SelectionInstruction &insn) {
const GenRegister header = GenRegister::retype(ra->genReg(insn.src(0)), GEN_TYPE_UD);
+ GenRegister data = ra->genReg(insn.src(5));
const uint32_t bti = insn.getbti();
- p->TYPED_WRITE(header, true, bti);
+ p->TYPED_WRITE(header, data, true, bti, insn.extra.typedWriteSplitSend);
}
static void calcGID(GenRegister& reg, GenRegister& tmp, int flag, int subFlag, int dim, GenContext *gc)
diff --git a/backend/src/backend/gen_encoder.cpp b/backend/src/backend/gen_encoder.cpp
index a9bdd3a..5dea48a 100644
--- a/backend/src/backend/gen_encoder.cpp
+++ b/backend/src/backend/gen_encoder.cpp
@@ -1257,7 +1257,7 @@ namespace gbe
msg_type, vme_search_path_lut, lut_sub);
}
- void GenEncoder::TYPED_WRITE(GenRegister msg, bool header_present, unsigned char bti)
+ void GenEncoder::TYPED_WRITE(GenRegister msg, GenRegister data, bool header_present, unsigned char bti, bool useSends)
{
GenNativeInstruction *insn = this->next(GEN_OPCODE_SEND);
uint32_t msg_type = GEN_TYPED_WRITE;
diff --git a/backend/src/backend/gen_encoder.hpp b/backend/src/backend/gen_encoder.hpp
index b86e9e4..66aa9cb 100644
--- a/backend/src/backend/gen_encoder.hpp
+++ b/backend/src/backend/gen_encoder.hpp
@@ -234,8 +234,10 @@ namespace gbe
/*! TypedWrite instruction for texture */
virtual void TYPED_WRITE(GenRegister header,
+ GenRegister data,
bool header_present,
- unsigned char bti);
+ unsigned char bti,
+ bool useSends);
/*! Extended math function (2 sources) */
void MATH(GenRegister dst, uint32_t function, GenRegister src0, GenRegister src1);
/*! Extended math function (1 source) */
diff --git a/backend/src/backend/gen_insn_selection.cpp b/backend/src/backend/gen_insn_selection.cpp
index ec0897c..90e3a14 100644
--- a/backend/src/backend/gen_insn_selection.cpp
+++ b/backend/src/backend/gen_insn_selection.cpp
@@ -2824,7 +2824,6 @@ extern bool OCL_DEBUGINFO; // first defined by calling BVAR in program.cpp
uint32_t elemID = 0;
uint32_t i;
SelectionInstruction *insn = this->appendInsn(SEL_OP_TYPED_WRITE, 0, msgNum);
- SelectionVector *msgVector = this->appendVector();;
for( i = 0; i < msgNum; ++i, ++elemID)
insn->src(elemID) = msgs[i];
@@ -2832,11 +2831,31 @@ extern bool OCL_DEBUGINFO; // first defined by calling BVAR in program.cpp
insn->setbti(bti);
insn->extra.msglen = msgNum;
insn->extra.is3DWrite = is3D;
- // Sends require contiguous allocation
- msgVector->regNum = msgNum;
- msgVector->isSrc = 1;
- msgVector->offsetID = 0;
- msgVector->reg = &insn->src(0);
+
+ if (hasSends()) {
+ assert(msgNum == 9);
+ insn->extra.typedWriteSplitSend = 1;
+ //header + coords
+ SelectionVector *msgVector = this->appendVector();
+ msgVector->regNum = 5;
+ msgVector->isSrc = 1;
+ msgVector->offsetID = 0;
+ msgVector->reg = &insn->src(0);
+
+ //data
+ msgVector = this->appendVector();
+ msgVector->regNum = 4;
+ msgVector->isSrc = 1;
+ msgVector->offsetID = 5;
+ msgVector->reg = &insn->src(5);
+ } else {
+ // Send require contiguous allocation
+ SelectionVector *msgVector = this->appendVector();
+ msgVector->regNum = msgNum;
+ msgVector->isSrc = 1;
+ msgVector->offsetID = 0;
+ msgVector->reg = &insn->src(0);
+ }
}
Selection::~Selection(void) { GBE_DELETE(this->opaque); }
diff --git a/backend/src/backend/gen_insn_selection.hpp b/backend/src/backend/gen_insn_selection.hpp
index 8ab0d07..01999a2 100644
--- a/backend/src/backend/gen_insn_selection.hpp
+++ b/backend/src/backend/gen_insn_selection.hpp
@@ -126,6 +126,7 @@ namespace gbe
uint16_t bti:8;
uint16_t msglen:5;
uint16_t is3DWrite:1;
+ uint16_t typedWriteSplitSend:1;
};
struct {
uint16_t rdbti:8;
--
1.9.1
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