[Beignet] [PATCH] GBE: fix a src/dst register reuse bug.

[Yang Rong]

For case:
 mad(8)          g4<1>:F         g4.1<0,1,0>:F   g127.7<0,1,0>:F g46:F
src0 is uniform, dst is non-uniform, dst can't reuse the src0.

Signed-off-by: Yang Rong <rong.r.yang at intel.com>
---
 backend/src/backend/gen_reg_allocation.cpp | 7 ++++++-
 backend/src/backend/gen_register.hpp       | 7 +++++++
 2 files changed, 13 insertions(+), 1 deletion(-)

diff --git a/backend/src/backend/gen_reg_allocation.cpp b/backend/src/backend/gen_reg_allocation.cpp
index 2b76eee..b65f702 100644
--- a/backend/src/backend/gen_reg_allocation.cpp
+++ b/backend/src/backend/gen_reg_allocation.cpp
@@ -1242,6 +1242,11 @@ namespace gbe
         const uint32_t srcNum = insn.srcNum, dstNum = insn.dstNum;
         assert(insnID == (int32_t)insn.ID);
         bool is3SrcOp = insn.opcode == SEL_OP_MAD;
+        bool isDstUniform = true;
+        for (uint32_t dstID = 0; dstID < dstNum; ++dstID) {
+          const GenRegister &selReg = insn.dst(dstID);
+          isDstUniform &= GenRegister::isUniform(selReg);
+        }
         for (uint32_t srcID = 0; srcID < srcNum; ++srcID) {
           const GenRegister &selReg = insn.src(srcID);
           const ir::Register reg = selReg.reg();
@@ -1267,7 +1272,7 @@ namespace gbe
           this->intervals[reg].conflictReg = conflictReg;
           int insnsrcID = insnID;
           // If instruction is simple, src and dst can be reused and they will have different IDs
-          if (insn.isNative())
+          if (insn.isNative() && GenRegister::isUniform(selReg) == isDstUniform)
             insnsrcID -= 1;
           this->intervals[reg].minID = std::min(this->intervals[reg].minID, insnsrcID);
           this->intervals[reg].maxID = std::max(this->intervals[reg].maxID, insnsrcID);
diff --git a/backend/src/backend/gen_register.hpp b/backend/src/backend/gen_register.hpp
index d9798cf..213bf05 100644
--- a/backend/src/backend/gen_register.hpp
+++ b/backend/src/backend/gen_register.hpp
@@ -293,6 +293,13 @@ namespace gbe
       return r;
     }
 
+    static INLINE bool isUniform(GenRegister reg) {
+      return reg.file == GEN_GENERAL_REGISTER_FILE &&
+             reg.hstride == GEN_HORIZONTAL_STRIDE_0 &&
+             reg.vstride == GEN_VERTICAL_STRIDE_0 &&
+             reg.width == GEN_WIDTH_1;
+    }
+
     static INLINE uint32_t grfOffset(GenRegister reg) {
       return reg.nr * GEN_REG_SIZE + reg.subnr;
     }
-- 
2.1.4