[Beignet] [PATCH] Revert "GBE: disable mad for some cases."

[Yang, Rong R]

Pushed, thanks.

> -----Original Message-----
> From: Beignet [mailto:beignet-bounces at lists.freedesktop.org] On Behalf Of
> Song, Ruiling
> Sent: Friday, February 19, 2016 16:43
> To: Gong, Zhigang <zhigang.gong at intel.com>;
> beignet at lists.freedesktop.org
> Cc: Gong, Zhigang <zhigang.gong at intel.com>
> Subject: Re: [Beignet] [PATCH] Revert "GBE: disable mad for some cases."
> 
> LGTM
> 
> Thanks!
> Ruiling
> > -----Original Message-----
> > From: Beignet [mailto:beignet-bounces at lists.freedesktop.org] On Behalf
> > Of Zhigang Gong
> > Sent: Friday, February 19, 2016 2:08 PM
> > To: beignet at lists.freedesktop.org
> > Cc: Gong, Zhigang <zhigang.gong at intel.com>
> > Subject: [Beignet] [PATCH] Revert "GBE: disable mad for some cases."
> >
> > This reverts commit d73170df3508d18e250d0af118e3b7955401194f.
> > Actually, MAD should be always faster if we can use it to replace
> > orignal Multiply + ADD. So let's revert this patch.
> >
> > Signed-off-by: Zhigang Gong <zhigang.gong at intel.com>
> > ---
> >  backend/src/backend/gen_insn_selection.cpp | 14 +-------------
> >  1 file changed, 1 insertion(+), 13 deletions(-)
> >
> > diff --git a/backend/src/backend/gen_insn_selection.cpp
> > b/backend/src/backend/gen_insn_selection.cpp
> > index 001a3c5..9225294 100644
> > --- a/backend/src/backend/gen_insn_selection.cpp
> > +++ b/backend/src/backend/gen_insn_selection.cpp
> > @@ -3111,7 +3111,7 @@ extern bool OCL_DEBUGINFO; // first defined by
> > calling BVAR in program.cpp
> >
> >        // XXX TODO: we need a clean support of FP_CONTRACT to remove
> > below line 'return false'
> >        // if 'pragma FP_CONTRACT OFF' is used in cl kernel, we should
> > not do mad optimization.
> > -      if (!sel.ctx.relaxMath || sel.ctx.getSimdWidth() == 16)
> > +      if (!sel.ctx.relaxMath)
> >          return false;
> >        // MAD tend to increase liveness of the sources (since there are three
> of
> >        // them). TODO refine this strategy. Well, we should be able at
> > least to @@ -3129,12 +3129,6 @@ extern bool OCL_DEBUGINFO; // first
> > defined by calling BVAR in program.cpp
> >        const GenRegister dst = sel.selReg(insn.getDst(0), TYPE_FLOAT);
> >        if (child0 && child0->insn.getOpcode() == OP_MUL) {
> >
> > GBE_ASSERT(cast<ir::BinaryInstruction>(child0->insn).getType() ==
> TYPE_FLOAT);
> > -        SelectionDAG *child00 = child0->child[0];
> > -        SelectionDAG *child01 = child0->child[1];
> > -        if ((child00 && child00->insn.getOpcode() == OP_LOADI) ||
> > -            (child01 && child01->insn.getOpcode() == OP_LOADI) ||
> > -            (child1 && child1->insn.getOpcode() == OP_LOADI))
> > -          return false;
> >          const GenRegister src0 = sel.selReg(child0->insn.getSrc(0),
> TYPE_FLOAT);
> >          const GenRegister src1 = sel.selReg(child0->insn.getSrc(1),
> TYPE_FLOAT);
> >          GenRegister src2 = sel.selReg(insn.getSrc(1), TYPE_FLOAT); @@
> > -3147,12 +3141,6 @@ extern bool OCL_DEBUGINFO; // first defined by
> > calling BVAR in program.cpp
> >        }
> >        if (child1 && child1->insn.getOpcode() == OP_MUL) {
> >
> > GBE_ASSERT(cast<ir::BinaryInstruction>(child1->insn).getType() ==
> TYPE_FLOAT);
> > -        SelectionDAG *child10 = child1->child[0];
> > -        SelectionDAG *child11 = child1->child[1];
> > -        if ((child10 && child10->insn.getOpcode() == OP_LOADI) ||
> > -            (child11 && child11->insn.getOpcode() == OP_LOADI) ||
> > -            (child0 && child0->insn.getOpcode() == OP_LOADI))
> > -          return false;
> >          GenRegister src0 = sel.selReg(child1->insn.getSrc(0), TYPE_FLOAT);
> >          const GenRegister src1 = sel.selReg(child1->insn.getSrc(1),
> TYPE_FLOAT);
> >          const GenRegister src2 = sel.selReg(insn.getSrc(0),
> > TYPE_FLOAT);
> > --
> > 2.5.0
> >
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