[Beignet] [PATCH 4/5] Backend: Optimization internal math, use mad

[Lupescu, Grigore]

Tests I did related to the log1p implementation showed the problem was from using mad(a,b,c) instead of a*b+c and not from an architecture change (i.e. IVB vs HSW or BDW). I am currently looking briefly for the reason in the drop of accuracy - also to completely exclude hardware.

-----Original Message-----
From: Song, Ruiling 
Sent: Monday, July 4, 2016 9:03 AM
To: Lupescu, Grigore <grigore.lupescu at intel.com>; Yang, Rong R <rong.r.yang at intel.com>; beignet at lists.freedesktop.org
Subject: RE: [Beignet] [PATCH 4/5] Backend: Optimization internal math, use mad



> -----Original Message-----
> From: Lupescu, Grigore
> Sent: Tuesday, June 28, 2016 2:58 AM
> To: Yang, Rong R <rong.r.yang at intel.com>; Song, Ruiling 
> <ruiling.song at intel.com>; beignet at lists.freedesktop.org
> Subject: RE: [Beignet] [PATCH 4/5] Backend: Optimization internal 
> math, use mad
> 
> The functions sinh, cosh, tanh and log1p were failing because log1p was failing.
> Log1p was failing due to translation of a*b+c in mad (a, b, c).
> I have fixed the log1p implementation. Errors were less in patch 5 
> (with CLC) because sinh, cosh don't use log1p in the CLC variant (as 
> oposed to patch 4 - fdlibm).
Sorry I don't quite understand, I remember the issue only occurs on IVB?
So do you mean that "mad" on IVB behave different from HSW or BDW?

Thanks!
Ruiling
> 
> I will repost only the first 4 patches. The CLC functions (patch 5) 
> can anytime be used on top of patch 4 if we are sure there are no copyright issues.
> 
> -----Original Message-----
> From: Yang, Rong R
> Sent: Friday, June 24, 2016 1:18 PM
> To: Lupescu, Grigore <grigore.lupescu at intel.com>; Song, Ruiling 
> <ruiling.song at intel.com>; beignet at lists.freedesktop.org
> Subject: RE: [Beignet] [PATCH 4/5] Backend: Optimization internal 
> math, use mad
> 
> Can you compare the LLVM IR/GEN IR/ASM between the IVB and HSW, use 
> same version llvm, maybe could quick find the root cause.
> 
> > -----Original Message-----
> > From: Lupescu, Grigore
> > Sent: Friday, June 24, 2016 1:16
> > To: Yang, Rong R <rong.r.yang at intel.com>; Song, Ruiling 
> > <ruiling.song at intel.com>; beignet at lists.freedesktop.org
> > Subject: RE: [Beignet] [PATCH 4/5] Backend: Optimization internal 
> > math, use mad
> >
> > I confirm some tests are failing for IVB architecture. I am looking 
> > into this issue.
> >
> > I ran the conformance on IVB i7-3770K (patchset 1,2,3,4 - without 
> > the patch 5
> > clc) which gave: FAILED 4 of 98 tests i.e. failed on log1p, atanh, cosh, sinh.
> > Changes to those functions are done in patch 4. Applying only first 
> > 3 patches results in all tests passing for IVB.
> >
> > I did not experience any of these failures on HSW or BDW architecture.
> >
> > -----Original Message-----
> > From: Yang, Rong R
> > Sent: Thursday, June 23, 2016 9:13 AM
> > To: Song, Ruiling <ruiling.song at intel.com>; Lupescu, Grigore 
> > <grigore.lupescu at intel.com>; beignet at lists.freedesktop.org
> > Subject: RE: [Beignet] [PATCH 4/5] Backend: Optimization internal 
> > math, use mad
> >
> > This patchset will cause some math utests fail in IVB, such as 
> > builtin_acos_asin, builtin_lgamma_float and so on.
> >
> > > -----Original Message-----
> > > From: Beignet [mailto:beignet-bounces at lists.freedesktop.org] On 
> > > Behalf Of Song, Ruiling
> > > Sent: Monday, June 6, 2016 16:39
> > > To: Lupescu, Grigore <grigore.lupescu at intel.com>; 
> > > beignet at lists.freedesktop.org
> > > Subject: Re: [Beignet] [PATCH 4/5] Backend: Optimization internal 
> > > math, use mad
> > >
> > > The first four patches look good. But personally I don't think the 
> > > 5th patch is proper for merge, although I am not good at copyright topics.
> > >
> > > Thanks!
> > > Ruiling
> > > _______________________________________________
> > > Beignet mailing list
> > > Beignet at lists.freedesktop.org
> > > https://lists.freedesktop.org/mailman/listinfo/beignet