[Beignet] [PATCH V2 08/15] Backend: Change the sel ir optimization for unpack register

[Xiuli Pan]

From: Pan Xiuli <xiuli.pan at intel.com>

To unpack UW we may need to add mov and we do not want this mov to be
optimizated by the sel ir optimization. Add check for hstrid to avoid
this kind optimization.

Signed-off-by: Pan Xiuli <xiuli.pan at intel.com>
---
 backend/src/backend/gen_insn_selection_optimize.cpp | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/backend/src/backend/gen_insn_selection_optimize.cpp b/backend/src/backend/gen_insn_selection_optimize.cpp
index b8aa776..56c7615 100644
--- a/backend/src/backend/gen_insn_selection_optimize.cpp
+++ b/backend/src/backend/gen_insn_selection_optimize.cpp
@@ -161,7 +161,7 @@ namespace gbe
     assert(insn.opcode == SEL_OP_MOV);
     const GenRegister& src = insn.src(0);
     const GenRegister& dst = insn.dst(0);
-    if (src.type != dst.type || src.file != dst.file)
+    if (src.type != dst.type || src.file != dst.file || src.hstride != dst.hstride)
       return;
 
     if (liveout.find(dst.reg()) != liveout.end())
-- 
2.7.4