[Beignet] [PATCH 5/6] Backend: Fix bug for sub/work group functions

[Xiuli Pan]

From: Pan Xiuli <xiuli.pan at intel.com>

In simd8 mode, some of the MOV is in simd16 mode, they will influence
registers that we should not access.

Signed-off-by: Pan Xiuli <xiuli.pan at intel.com>
---
 backend/src/backend/gen8_context.cpp | 14 +++++++-------
 backend/src/backend/gen_context.cpp  | 14 +++++++-------
 2 files changed, 14 insertions(+), 14 deletions(-)

diff --git a/backend/src/backend/gen8_context.cpp b/backend/src/backend/gen8_context.cpp
index a520e61..09b38b2 100644
--- a/backend/src/backend/gen8_context.cpp
+++ b/backend/src/backend/gen8_context.cpp
@@ -1590,7 +1590,7 @@ namespace gbe
        wg_op == ir::WORKGROUP_OP_REDUCE_MIN ||
        wg_op == ir::WORKGROUP_OP_REDUCE_MAX)
    {
-     p->curr.execWidth = 16;
+     p->curr.execWidth = simd;
      /* value exchanged with other threads */
      p->MOV(threadExchangeData, result[0]);
      /* partial result thread */
@@ -1600,7 +1600,7 @@ namespace gbe
        wg_op == ir::WORKGROUP_OP_INCLUSIVE_MIN ||
        wg_op == ir::WORKGROUP_OP_INCLUSIVE_MAX)
    {
-     p->curr.execWidth = 16;
+     p->curr.execWidth = simd;
      /* value exchanged with other threads */
      p->MOV(threadExchangeData, result[simd - 1]);
      /* partial result thread */
@@ -1614,7 +1614,7 @@ namespace gbe
      /* set result[0] to min/max/null */
      wgOpInitValue(p, result[0], wg_op);
 
-     p->curr.execWidth = 16;
+     p->curr.execWidth = simd;
      /* value exchanged with other threads */
      wgOpPerform(threadExchangeData, result[simd - 1], input[simd - 1], wg_op, p);
      /* partial result thread */
@@ -1675,7 +1675,7 @@ namespace gbe
     /* do some calculation within each thread */
     wgOpPerformThread(dst, theVal, threadData, tmp, simd, wg_op, p);
 
-    p->curr.execWidth = 16;
+    p->curr.execWidth = simd;
     p->MOV(theVal, dst);
     threadData = GenRegister::toUniform(threadData, dst.type);
 
@@ -1790,13 +1790,13 @@ namespace gbe
       wg_op == ir::WORKGROUP_OP_REDUCE_MAX)
     {
       /* save result to final register location dst */
-      p->curr.execWidth = 16;
+      p->curr.execWidth = simd;
       p->MOV(dst, partialData);
     }
     else
     {
       /* save result to final register location dst */
-      p->curr.execWidth = 16;
+      p->curr.execWidth = simd;
 
       if(wg_op == ir::WORKGROUP_OP_INCLUSIVE_ADD
           || wg_op == ir::WORKGROUP_OP_EXCLUSIVE_ADD)
@@ -1845,7 +1845,7 @@ namespace gbe
         p->CMP(GEN_CONDITIONAL_EQ, threadId, GenRegister::immd(0x0));
         p->curr.predicate = GEN_PREDICATE_NORMAL;
 
-        p->curr.execWidth = 16;
+        p->curr.execWidth = simd;
         p->MOV(dst, theVal);
       } p->pop();
     }
diff --git a/backend/src/backend/gen_context.cpp b/backend/src/backend/gen_context.cpp
index 6afa470..4f73237 100644
--- a/backend/src/backend/gen_context.cpp
+++ b/backend/src/backend/gen_context.cpp
@@ -3113,7 +3113,7 @@ namespace gbe
        wg_op == ir::WORKGROUP_OP_REDUCE_MIN ||
        wg_op == ir::WORKGROUP_OP_REDUCE_MAX)
    {
-     p->curr.execWidth = 16;
+     p->curr.execWidth = simd;
      /* value exchanged with other threads */
      p->MOV(threadExchangeData, result[0]);
      /* partial result thread */
@@ -3123,7 +3123,7 @@ namespace gbe
        wg_op == ir::WORKGROUP_OP_INCLUSIVE_MIN ||
        wg_op == ir::WORKGROUP_OP_INCLUSIVE_MAX)
    {
-     p->curr.execWidth = 16;
+     p->curr.execWidth = simd;
      /* value exchanged with other threads */
      p->MOV(threadExchangeData, result[simd - 1]);
      /* partial result thread */
@@ -3137,7 +3137,7 @@ namespace gbe
      /* set result[0] to min/max/null */
      wgOpInitValue(p, result[0], wg_op);
 
-     p->curr.execWidth = 16;
+     p->curr.execWidth = simd;
      /* value exchanged with other threads */
      wgOpPerform(threadExchangeData, result[simd - 1], input[simd - 1], wg_op, p);
      /* partial result thread */
@@ -3198,7 +3198,7 @@ namespace gbe
     /* do some calculation within each thread */
     wgOpPerformThread(dst, theVal, threadData, tmp, simd, wg_op, p);
 
-    p->curr.execWidth = 16;
+    p->curr.execWidth = simd;
     p->MOV(theVal, dst);
     threadData = GenRegister::toUniform(threadData, dst.type);
 
@@ -3313,13 +3313,13 @@ namespace gbe
       wg_op == ir::WORKGROUP_OP_REDUCE_MAX)
     {
       /* save result to final register location dst */
-      p->curr.execWidth = 16;
+      p->curr.execWidth = simd;
       p->MOV(dst, partialData);
     }
     else
     {
       /* save result to final register location dst */
-      p->curr.execWidth = 16;
+      p->curr.execWidth = simd;
 
       if(wg_op == ir::WORKGROUP_OP_INCLUSIVE_ADD
           || wg_op == ir::WORKGROUP_OP_EXCLUSIVE_ADD)
@@ -3368,7 +3368,7 @@ namespace gbe
         p->CMP(GEN_CONDITIONAL_EQ, threadId, GenRegister::immd(0x0));
         p->curr.predicate = GEN_PREDICATE_NORMAL;
 
-        p->curr.execWidth = 16;
+        p->curr.execWidth = simd;
         p->MOV(dst, theVal);
       } p->pop();
     }
-- 
2.7.4