[Beignet] [PATCH V3] Backend: Refine gen ir ALU1 inst getType

[Yang, Rong R]

LGTM, thanks, will push it.

> -----Original Message-----
> From: Beignet [mailto:beignet-bounces at lists.freedesktop.org] On Behalf Of
> Xiuli Pan
> Sent: Monday, September 5, 2016 14:53
> To: beignet at lists.freedesktop.org
> Cc: Pan, Xiuli <xiuli.pan at intel.com>
> Subject: [Beignet] [PATCH V3] Backend: Refine gen ir ALU1 inst getType
> 
> From: Pan Xiuli <xiuli.pan at intel.com>
> 
> ALU1 getType function used to override some inst type, refine it by set the
> right type for these ALU1 inst.
> This will fix MOV for half and double type.
> V2: Keep the optimization for MOV with float type.
> V3: Add more check to make optimization only apply for MOV
> 
> Signed-off-by: Pan Xiuli <xiuli.pan at intel.com>
> ---
>  backend/src/backend/gen_insn_selection.cpp | 13 ++++---------
>  backend/src/llvm/llvm_gen_backend.cpp      |  9 +++++----
>  2 files changed, 9 insertions(+), 13 deletions(-)
> 
> diff --git a/backend/src/backend/gen_insn_selection.cpp
> b/backend/src/backend/gen_insn_selection.cpp
> index 3b21fb5..284e2c7 100644
> --- a/backend/src/backend/gen_insn_selection.cpp
> +++ b/backend/src/backend/gen_insn_selection.cpp
> @@ -2786,17 +2786,12 @@ extern bool OCL_DEBUGINFO; // first defined by
> calling BVAR in program.cpp
>      static ir::Type getType(const ir::Opcode opcode, const ir::Type insnType,
> bool isSrc = false) {
>        if (opcode == ir::OP_CBIT)
>          return isSrc ? insnType : ir::TYPE_U32;
> -      if (insnType == ir::TYPE_S64 || insnType == ir::TYPE_U64 || insnType ==
> ir::TYPE_S8 || insnType == ir::TYPE_U8)
> -        return insnType;
> -      if (opcode == ir::OP_FBH || opcode == ir::OP_FBL || opcode ==
> ir::OP_LZD)
> -        return ir::TYPE_U32;
> -      if (opcode == ir::OP_SIMD_ANY || opcode == ir::OP_SIMD_ALL)
> -        return ir::TYPE_S32;
> -      if (insnType == ir::TYPE_S16 || insnType == ir::TYPE_U16)
> -        return insnType;
>        if (insnType == ir::TYPE_BOOL)
>          return ir::TYPE_U16;
> -      return ir::TYPE_FLOAT;
> +      else if (opcode == ir::OP_MOV && (insnType == ir::TYPE_U32 ||
> insnType == ir::TYPE_S32))
> +        return ir::TYPE_FLOAT;
> +      else
> +        return insnType;
>      }
> 
>      INLINE bool emitOne(Selection::Opaque &sel, const ir::UnaryInstruction
> &insn, bool &markChildren) const { diff --git
> a/backend/src/llvm/llvm_gen_backend.cpp
> b/backend/src/llvm/llvm_gen_backend.cpp
> index 5135950..7005d60 100644
> --- a/backend/src/llvm/llvm_gen_backend.cpp
> +++ b/backend/src/llvm/llvm_gen_backend.cpp
> @@ -4195,13 +4195,14 @@ namespace gbe
>                ir::Register tmp1 = ctx.reg(getFamily(tmpType));
>                ir::Register tmp2 = ctx.reg(getFamily(tmpType));
>                ctx.CVT(tmpType, srcType, tmp0, src);
> -              ctx.ALU1(ir::OP_LZD, tmpType, tmp1, tmp0);
> +              ctx.ALU1(ir::OP_LZD, ir::TYPE_U32, tmp1, tmp0);
>                ctx.SUB(tmpType, tmp2, tmp1, immReg);
>                ctx.CVT(dstType, tmpType, dst, tmp2);
>              }
>              else
>              {
> -              ctx.ALU1(ir::OP_LZD, dstType, dst, src);
> +              GBE_ASSERT(srcType == ir::TYPE_U32);
> +              ctx.ALU1(ir::OP_LZD, srcType, dst, src);
>              }
>            }
>            break;
> @@ -4258,8 +4259,8 @@ namespace gbe
>  #endif /* GBE_DEBUG */
> 
>          switch (genIntrinsicID) {
> -          case GEN_OCL_FBH: this->emitUnaryCallInst(I,CS,ir::OP_FBH); break;
> -          case GEN_OCL_FBL: this->emitUnaryCallInst(I,CS,ir::OP_FBL); break;
> +          case GEN_OCL_FBH: this->emitUnaryCallInst(I,CS,ir::OP_FBH,
> ir::TYPE_U32); break;
> +          case GEN_OCL_FBL: this->emitUnaryCallInst(I,CS,ir::OP_FBL,
> + ir::TYPE_U32); break;
>            case GEN_OCL_CBIT: this->emitUnaryCallInst(I,CS,ir::OP_CBIT,
> getUnsignedType(ctx, (*AI)->getType())); break;
>            case GEN_OCL_ABS:
>            {
> --
> 2.7.4
> 
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