[Beignet] [PATCH 1/2] add bxt with pciid 0x1A85
Guo Yejun
yejun.guo at intel.com
Fri Sep 30 02:37:25 UTC 2016
contributor: Curfman, Matthew C <matthew.c.curfman at intel.com>
Signed-off-by: Guo Yejun <yejun.guo at intel.com>
---
src/cl_device_data.h | 4 +++-
src/cl_device_id.c | 34 ++++++++++++++++++----------------
src/intel/intel_driver.c | 3 ++-
src/intel/intel_gpgpu.c | 3 ++-
4 files changed, 25 insertions(+), 19 deletions(-)
diff --git a/src/cl_device_data.h b/src/cl_device_data.h
index a237b0e..3e6ac91 100644
--- a/src/cl_device_data.h
+++ b/src/cl_device_data.h
@@ -300,11 +300,13 @@
#define PCI_CHIP_BROXTON_P 0x5A84 /* Intel(R) BXT-P for mobile desktop */
#define PCI_CHIP_BROXTON_1 0x5A85
#define PCI_CHIP_BROXTON_2 0x1A84
+#define PCI_CHIP_BROXTON_3 0x1A85
#define IS_BROXTON(devid) \
(devid == PCI_CHIP_BROXTON_P || \
devid == PCI_CHIP_BROXTON_1 || \
- devid == PCI_CHIP_BROXTON_2)
+ devid == PCI_CHIP_BROXTON_2 || \
+ devid == PCI_CHIP_BROXTON_3)
#define PCI_CHIP_KABYLAKE_ULT_GT1 0x5906
#define PCI_CHIP_KABYLAKE_ULT_GT2 0x5916
diff --git a/src/cl_device_id.c b/src/cl_device_id.c
index 02aad96..19f984f 100644
--- a/src/cl_device_id.c
+++ b/src/cl_device_id.c
@@ -185,7 +185,7 @@ static struct _cl_device_id intel_skl_gt4_device = {
#include "cl_gen9_device.h"
};
-static struct _cl_device_id intel_bxt_device = {
+static struct _cl_device_id intel_bxt18eu_device = {
.max_compute_unit = 18,
.max_thread_per_unit = 6,
.sub_slice_count = 3,
@@ -195,7 +195,7 @@ static struct _cl_device_id intel_bxt_device = {
#include "cl_gen9_device.h"
};
-static struct _cl_device_id intel_bxt1_device = {
+static struct _cl_device_id intel_bxt12eu_device = {
.max_compute_unit = 12,
.max_thread_per_unit = 6,
.sub_slice_count = 2,
@@ -616,23 +616,25 @@ skl_gt4_break:
break;
case PCI_CHIP_BROXTON_P:
- DECL_INFO_STRING(bxt_break, intel_bxt_device, name, "Intel(R) HD Graphics Broxton-P");
+ DECL_INFO_STRING(bxt18eu_break, intel_bxt18eu_device, name, "Intel(R) HD Graphics Broxton-P");
case PCI_CHIP_BROXTON_2:
- DECL_INFO_STRING(bxt_break, intel_bxt_device, name, "Intel(R) HD Graphics Broxton 2");
-bxt_break:
- intel_bxt_device.device_id = device_id;
- intel_bxt_device.platform = cl_get_platform_default();
- ret = &intel_bxt_device;
+ DECL_INFO_STRING(bxt18eu_break, intel_bxt18eu_device, name, "Intel(R) HD Graphics Broxton 2");
+bxt18eu_break:
+ intel_bxt18eu_device.device_id = device_id;
+ intel_bxt18eu_device.platform = cl_get_platform_default();
+ ret = &intel_bxt18eu_device;
cl_intel_platform_get_default_extension(ret);
cl_intel_platform_enable_extension(ret, cl_khr_fp16_ext_id);
break;
case PCI_CHIP_BROXTON_1:
- DECL_INFO_STRING(bxt1_break, intel_bxt1_device, name, "Intel(R) HD Graphics Broxton 1");
-bxt1_break:
- intel_bxt1_device.device_id = device_id;
- intel_bxt1_device.platform = cl_get_platform_default();
- ret = &intel_bxt1_device;
+ DECL_INFO_STRING(bxt12eu_break, intel_bxt12eu_device, name, "Intel(R) HD Graphics Broxton 1");
+ case PCI_CHIP_BROXTON_3:
+ DECL_INFO_STRING(bxt12eu_break, intel_bxt12eu_device, name, "Intel(R) HD Graphics Broxton 3");
+bxt12eu_break:
+ intel_bxt12eu_device.device_id = device_id;
+ intel_bxt12eu_device.platform = cl_get_platform_default();
+ ret = &intel_bxt12eu_device;
cl_intel_platform_get_default_extension(ret);
cl_intel_platform_enable_extension(ret, cl_khr_fp16_ext_id);
break;
@@ -952,8 +954,8 @@ LOCAL cl_bool is_gen_device(cl_device_id device) {
device == &intel_skl_gt2_device ||
device == &intel_skl_gt3_device ||
device == &intel_skl_gt4_device ||
- device == &intel_bxt_device ||
- device == &intel_bxt1_device ||
+ device == &intel_bxt18eu_device ||
+ device == &intel_bxt12eu_device ||
device == &intel_kbl_gt1_device ||
device == &intel_kbl_gt15_device ||
device == &intel_kbl_gt2_device ||
@@ -1097,7 +1099,7 @@ cl_device_get_version(cl_device_id device, cl_int *ver)
*ver = 8;
} else if (device == &intel_skl_gt1_device || device == &intel_skl_gt2_device
|| device == &intel_skl_gt3_device || device == &intel_skl_gt4_device
- || device == &intel_bxt_device || device == &intel_bxt1_device || device == &intel_kbl_gt1_device
+ || device == &intel_bxt18eu_device || device == &intel_bxt12eu_device || device == &intel_kbl_gt1_device
|| device == &intel_kbl_gt2_device || device == &intel_kbl_gt3_device
|| device == &intel_kbl_gt4_device || device == &intel_kbl_gt15_device) {
*ver = 9;
diff --git a/src/intel/intel_driver.c b/src/intel/intel_driver.c
index f503b55..5f4afda 100644
--- a/src/intel/intel_driver.c
+++ b/src/intel/intel_driver.c
@@ -469,7 +469,8 @@ intel_driver_enlarge_stack_size(struct intel_driver *drv, int32_t *stack_size)
{
if (drv->gen_ver == 75)
*stack_size = *stack_size * 4;
- else if (drv->device_id == PCI_CHIP_BROXTON_1 || IS_CHERRYVIEW(drv->device_id))
+ else if (drv->device_id == PCI_CHIP_BROXTON_1 || drv->device_id == PCI_CHIP_BROXTON_3 ||
+ IS_CHERRYVIEW(drv->device_id))
*stack_size = *stack_size * 2;
}
diff --git a/src/intel/intel_gpgpu.c b/src/intel/intel_gpgpu.c
index f8eac56..31e3573 100644
--- a/src/intel/intel_gpgpu.c
+++ b/src/intel/intel_gpgpu.c
@@ -1538,7 +1538,8 @@ intel_gpgpu_set_scratch(intel_gpgpu_t * gpgpu, uint32_t per_thread_size)
drm_intel_bo* old = gpgpu->scratch_b.bo;
uint32_t total = per_thread_size * gpgpu->max_threads;
/* Per Bspec, scratch should 2X the desired size when EU index is not continuous */
- if (IS_HASWELL(gpgpu->drv->device_id) || IS_CHERRYVIEW(gpgpu->drv->device_id) || PCI_CHIP_BROXTON_1 == gpgpu->drv->device_id)
+ if (IS_HASWELL(gpgpu->drv->device_id) || IS_CHERRYVIEW(gpgpu->drv->device_id) ||
+ PCI_CHIP_BROXTON_1 == gpgpu->drv->device_id || PCI_CHIP_BROXTON_3 == gpgpu->drv->device_id)
total *= 2;
gpgpu->per_thread_scratch = per_thread_size;
--
2.7.4
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