[Beignet] [PATCH] Backend: for BDW and after, According to BSpec no need to split CMP when src is DW DF

[Song, Ruiling]

> -----Original Message-----
> From: Beignet [mailto:beignet-bounces at lists.freedesktop.org] On Behalf Of
> rander
> Sent: Friday, February 17, 2017 10:42 AM
> To: beignet at lists.freedesktop.org
> Cc: Wang, Rander <rander.wang at intel.com>
> Subject: [Beignet] [PATCH] Backend: for BDW and after, According to BSpec no
> need to split CMP when src is DW DF
> 
> Signed-off-by: rander <rander.wang at intel.com>
> ---
>  backend/src/backend/gen8_encoder.cpp | 130
> +++++++++++++++++++++++++++++++++++
>  backend/src/backend/gen8_encoder.hpp |   1 +
>  backend/src/backend/gen_encoder.hpp  |   2 +-
>  3 files changed, 132 insertions(+), 1 deletion(-)
> 
> diff --git a/backend/src/backend/gen8_encoder.cpp
> b/backend/src/backend/gen8_encoder.cpp
> index a33fbac..0b0f4ea 100644
> --- a/backend/src/backend/gen8_encoder.cpp
> +++ b/backend/src/backend/gen8_encoder.cpp
> @@ -37,6 +37,7 @@ static const uint32_t untypedRWMask[] = {
> 
>  namespace gbe
>  {
> +  extern bool compactAlu2(GenEncoder *p, uint32_t opcode, GenRegister dst,
> GenRegister src0, GenRegister src1, uint32_t condition, bool split);
>    extern bool compactAlu3(GenEncoder *p, uint32_t opcode, GenRegister dst,
> GenRegister src0, GenRegister src1, GenRegister src2);
>    void Gen8Encoder::setHeader(GenNativeInstruction *insn) {
>      Gen8NativeInstruction *gen8_insn = &insn->gen8_insn;
> @@ -883,4 +884,133 @@ namespace gbe
>                     msg_length,
>                     response_length);
>     }
> +
> +  INLINE bool isVectorOfBytes(GenRegister reg) {
> +    if (reg.hstride != GEN_HORIZONTAL_STRIDE_0 &&
> +        (reg.type == GEN_TYPE_UB || reg.type == GEN_TYPE_B))
> +      return true;
> +    else
> +      return false;
> +  }
> +
> +  INLINE bool isVectorOfLongs(GenRegister reg) {
> +    if (reg.hstride != GEN_HORIZONTAL_STRIDE_0 &&
> +        (reg.type == GEN_TYPE_UL || reg.type == GEN_TYPE_L))
> +      return true;
> +    else
> +      return false;
> +  }
> +
> +  INLINE bool isCrossMoreThan2(GenRegister reg) {
> +    if (reg.hstride == GEN_HORIZONTAL_STRIDE_0)
> +      return false;
> +
> +    const uint32_t typeSz = typeSize(reg.type);
> +    const uint32_t horizontal = stride(reg.hstride);
> +    if (horizontal * typeSz * 16 > GEN_REG_SIZE * 2) {
> +      return true;
> +    }
> +    return false;
> +  }
> +
> +  INLINE bool isSrcDstDiffSpan(GenRegister dst, GenRegister src) {
> +    if (src.hstride == GEN_HORIZONTAL_STRIDE_0) return false;
> +
> +    GBE_ASSERT(dst.hstride != GEN_HORIZONTAL_STRIDE_0 && "dst register is
> uniform but src is not.");
> +
> +    uint32_t typeSz = typeSize(dst.type);
> +    uint32_t horizontal = stride(dst.hstride);
> +    uint32_t spans = (dst.subnr / (horizontal * typeSz)) * (horizontal * typeSz)  +
> horizontal * typeSz * 16;
> +    uint32_t dstSpan = spans / GEN_REG_SIZE;
> +    dstSpan = dstSpan + (spans % GEN_REG_SIZE == 0 ? 0 : 1);
> +    if (dstSpan < 2) return false;
> +
> +    typeSz = typeSize(src.type);
> +    horizontal = stride(src.hstride);
> +    spans = (src.subnr / (horizontal * typeSz)) * (horizontal * typeSz)  + horizontal
> * typeSz * 16;
> +    uint32_t srcSpan = (horizontal * typeSz * 16) / GEN_REG_SIZE;
> +    srcSpan = srcSpan + (spans % GEN_REG_SIZE == 0 ? 0 : 1);
> +
> +    GBE_ASSERT(srcSpan <= 2);
> +    GBE_ASSERT(dstSpan == 2);
> +
> +    if (srcSpan == dstSpan) return false;
> +
> +    /* Special case, dst is DW and src is w.
> +       the case:
> +       mov (16) r10.0<1>:d r12<8;8,1>:w
> +       is allowed. */
> +    if ((dst.type == GEN_TYPE_UD || dst.type == GEN_TYPE_D)
> +          && (src.type == GEN_TYPE_UW || src.type == GEN_TYPE_W)
> +          && dstSpan == 2 && srcSpan == 1
> +          && dst.subnr == 0 && src.subnr == 0) return false;
> +
> +    return true;
> +  }
> +
The above functions copied from gen_encoder.cpp?
If yes, I think you can make them virtual member functions of GenEncoder other than duplicating them.

Ruiling