[Beignet] [PATCH] Backend: Fix a selection ir optimization bug

[Yang, Rong R]

LGTM, will push it later, thanks.

> -----Original Message-----
> From: Beignet [mailto:beignet-bounces at lists.freedesktop.org] On Behalf Of
> Xiuli Pan
> Sent: Monday, February 27, 2017 11:16
> To: beignet at lists.freedesktop.org
> Cc: Pan, Xiuli <xiuli.pan at intel.com>
> Subject: [Beignet] [PATCH] Backend: Fix a selection ir optimization bug
> 
> From: Pan Xiuli <xiuli.pan at intel.com>
> 
> We used to check for unpacked instructions, but we will also ignore some
> patterns like:
> 
> MOV %1, %2.1
> MUL %4, %3, %1
> ==>
> MUL $4, %3, %2.1
> 
> Add more check to keep this kind of optimization.
> 
> Signed-off-by: Pan Xiuli <xiuli.pan at intel.com>
> ---
>  backend/src/backend/gen_insn_selection_optimize.cpp | 5 ++++-
>  1 file changed, 4 insertions(+), 1 deletion(-)
> 
> diff --git a/backend/src/backend/gen_insn_selection_optimize.cpp
> b/backend/src/backend/gen_insn_selection_optimize.cpp
> index 512a5bd..d2e0fb9 100644
> --- a/backend/src/backend/gen_insn_selection_optimize.cpp
> +++ b/backend/src/backend/gen_insn_selection_optimize.cpp
> @@ -162,7 +162,10 @@ namespace gbe
>      assert(insn.opcode == SEL_OP_MOV);
>      const GenRegister& src = insn.src(0);
>      const GenRegister& dst = insn.dst(0);
> -    if (src.type != dst.type || src.file != dst.file || src.hstride != dst.hstride)
> +    if (src.type != dst.type || src.file != dst.file)
> +      return;
> +
> +    if (src.hstride != GEN_HORIZONTAL_STRIDE_0 && src.hstride !=
> + dst.hstride )
>        return;
> 
>      if (liveout.find(dst.reg()) != liveout.end())
> --
> 2.7.4
> 
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