[Beignet] [PATCH 1/7] Backend: Fix flag and subflag seting for src 3 instruction

[Xiuli Pan]

From: Pan Xiuli <xiuli.pan at intel.com>

Before gen8, src 3 instruction has different flag and subflag bits

Signed-off-by: Pan Xiuli <xiuli.pan at intel.com>
---
 backend/src/backend/gen75_encoder.cpp    | 10 ++++++++--
 backend/src/backend/gen7_encoder.cpp     | 10 ++++++++--
 backend/src/backend/gen7_instruction.hpp |  5 +++--
 3 files changed, 19 insertions(+), 6 deletions(-)

diff --git a/backend/src/backend/gen75_encoder.cpp b/backend/src/backend/gen75_encoder.cpp
index b82cc43..06cca3c 100644
--- a/backend/src/backend/gen75_encoder.cpp
+++ b/backend/src/backend/gen75_encoder.cpp
@@ -53,8 +53,14 @@ namespace gbe
     gen7_insn->header.quarter_control = this->curr.quarterControl;
     gen7_insn->bits1.ia1.nib_ctrl = this->curr.nibControl;
     gen7_insn->header.mask_control = this->curr.noMask;
-    gen7_insn->bits2.ia1.flag_reg_nr = this->curr.flag;
-    gen7_insn->bits2.ia1.flag_sub_reg_nr = this->curr.subFlag;
+    if (insn->header.opcode == GEN_OPCODE_MAD || insn->header.opcode == GEN_OPCODE_LRP)
+    {
+      gen7_insn->bits1.da3src.flag_reg_nr = this->curr.flag;
+      gen7_insn->bits1.da3src.flag_sub_reg_nr = this->curr.subFlag;
+    } else {
+      gen7_insn->bits2.ia1.flag_reg_nr = this->curr.flag;
+      gen7_insn->bits2.ia1.flag_sub_reg_nr = this->curr.subFlag;
+    }
     if (this->curr.predicate != GEN_PREDICATE_NONE) {
       gen7_insn->header.predicate_control = this->curr.predicate;
       gen7_insn->header.predicate_inverse = this->curr.inversePredicate;
diff --git a/backend/src/backend/gen7_encoder.cpp b/backend/src/backend/gen7_encoder.cpp
index 4b2cd9a..d526f5d 100644
--- a/backend/src/backend/gen7_encoder.cpp
+++ b/backend/src/backend/gen7_encoder.cpp
@@ -46,8 +46,14 @@ namespace gbe
     gen7_insn->header.quarter_control = this->curr.quarterControl;
     gen7_insn->bits1.ia1.nib_ctrl = this->curr.nibControl;
     gen7_insn->header.mask_control = this->curr.noMask;
-    gen7_insn->bits2.ia1.flag_reg_nr = this->curr.flag;
-    gen7_insn->bits2.ia1.flag_sub_reg_nr = this->curr.subFlag;
+    if (insn->header.opcode == GEN_OPCODE_MAD || insn->header.opcode == GEN_OPCODE_LRP)
+    {
+      gen7_insn->bits1.da3src.flag_reg_nr = this->curr.flag;
+      gen7_insn->bits1.da3src.flag_sub_reg_nr = this->curr.subFlag;
+    } else {
+      gen7_insn->bits2.ia1.flag_reg_nr = this->curr.flag;
+      gen7_insn->bits2.ia1.flag_sub_reg_nr = this->curr.subFlag;
+    }
     if (this->curr.predicate != GEN_PREDICATE_NONE) {
       gen7_insn->header.predicate_control = this->curr.predicate;
       gen7_insn->header.predicate_inverse = this->curr.inversePredicate;
diff --git a/backend/src/backend/gen7_instruction.hpp b/backend/src/backend/gen7_instruction.hpp
index 7d7eada..4dc5b32 100644
--- a/backend/src/backend/gen7_instruction.hpp
+++ b/backend/src/backend/gen7_instruction.hpp
@@ -142,8 +142,9 @@ union Gen7NativeInstruction
 
       struct {
         uint32_t dest_reg_file:1;
-        uint32_t flag_subreg_num:1;
-        uint32_t pad0:2;
+        uint32_t flag_sub_reg_nr:1;
+        uint32_t pad0:1;
+        uint32_t flag_reg_nr:1;
         uint32_t src0_abs:1;
         uint32_t src0_negate:1;
         uint32_t src1_abs:1;
-- 
2.7.4