[Beignet] [PATCH 1/3] GLK: add Geminilake pciids.

[Yang Rong]

Signed-off-by: Yang Rong <rong.r.yang at intel.com>
---
 src/cl_device_data.h | 9 ++++++++-
 1 file changed, 8 insertions(+), 1 deletion(-)

diff --git a/src/cl_device_data.h b/src/cl_device_data.h
index f3c5204..39d3e2d 100644
--- a/src/cl_device_data.h
+++ b/src/cl_device_data.h
@@ -361,7 +361,14 @@
 
 #define IS_KABYLAKE(devid) (IS_KBL_GT1(devid) || IS_KBL_GT15(devid) || IS_KBL_GT2(devid) || IS_KBL_GT3(devid) || IS_KBL_GT4(devid))
 
-#define IS_GEN9(devid)     (IS_SKYLAKE(devid) || IS_BROXTON(devid) || IS_KABYLAKE(devid))
+#define PCI_CHIP_GLK         0x3184
+#define PCI_CHIP_GLK_2x6     0x3185
+
+#define IS_GEMINILAKE(devid)  \
+  (devid == PCI_CHIP_GLK ||   \
+   devid == PCI_CHIP_GLK_2x6)
+
+#define IS_GEN9(devid)     (IS_SKYLAKE(devid) || IS_BROXTON(devid) || IS_KABYLAKE(devid) || IS_GEMINILAKE(devid))
 
 #define MAX_OCLVERSION(devid) (IS_GEN9(devid) ? 200 : 120)
 
-- 
2.1.4