[Beignet] [PATCH 3/3] GLK: add geminilake runtime support.
Yang, Rong R
rong.r.yang at intel.com
Tue May 16 02:43:03 UTC 2017
Pushed, thanks.
> -----Original Message-----
> From: Pan, Xiuli
> Sent: Monday, May 15, 2017 15:05
> To: Yang, Rong R <rong.r.yang at intel.com>; beignet at lists.freedesktop.org
> Cc: Yang, Rong R <rong.r.yang at intel.com>
> Subject: RE: [Beignet] [PATCH 3/3] GLK: add geminilake runtime support.
>
> LGTM.
> Thanks
>
> -----Original Message-----
> From: Beignet [mailto:beignet-bounces at lists.freedesktop.org] On Behalf Of
> Yang Rong
> Sent: Monday, May 15, 2017 16:33
> To: beignet at lists.freedesktop.org
> Cc: Yang, Rong R <rong.r.yang at intel.com>
> Subject: [Beignet] [PATCH 3/3] GLK: add geminilake runtime support.
>
> Geminilake is almost same as bxt, except intel_gpgpu_read_ts_reg function.
>
> Signed-off-by: Yang Rong <rong.r.yang at intel.com>
> ---
> src/cl_device_data.h | 6 +++---
> src/cl_device_id.c | 47
> +++++++++++++++++++++++++++++++++++++++++++++--
> src/intel/intel_gpgpu.c | 2 ++
> 3 files changed, 50 insertions(+), 5 deletions(-)
>
> diff --git a/src/cl_device_data.h b/src/cl_device_data.h index
> 39d3e2d..c3d6c45 100644
> --- a/src/cl_device_data.h
> +++ b/src/cl_device_data.h
> @@ -361,11 +361,11 @@
>
> #define IS_KABYLAKE(devid) (IS_KBL_GT1(devid) || IS_KBL_GT15(devid) ||
> IS_KBL_GT2(devid) || IS_KBL_GT3(devid) || IS_KBL_GT4(devid))
>
> -#define PCI_CHIP_GLK 0x3184
> +#define PCI_CHIP_GLK_3x6 0x3184
> #define PCI_CHIP_GLK_2x6 0x3185
>
> -#define IS_GEMINILAKE(devid) \
> - (devid == PCI_CHIP_GLK || \
> +#define IS_GEMINILAKE(devid) \
> + (devid == PCI_CHIP_GLK_3x6 || \
> devid == PCI_CHIP_GLK_2x6)
>
> #define IS_GEN9(devid) (IS_SKYLAKE(devid) || IS_BROXTON(devid) ||
> IS_KABYLAKE(devid) || IS_GEMINILAKE(devid))
> diff --git a/src/cl_device_id.c b/src/cl_device_id.c index 50ed0d9..6cba2b5
> 100644
> --- a/src/cl_device_id.c
> +++ b/src/cl_device_id.c
> @@ -254,6 +254,26 @@ static struct _cl_device_id intel_kbl_gt4_device =
> { #include "cl_gen9_device.h"
> };
>
> +static struct _cl_device_id intel_glk18eu_device = {
> + .max_compute_unit = 18,
> + .max_thread_per_unit = 6,
> + .sub_slice_count = 3,
> + .max_work_item_sizes = {512, 512, 512},
> + .max_work_group_size = 512,
> + .max_clock_frequency = 1000,
> +#include "cl_gen9_device.h"
> +};
> +
> +static struct _cl_device_id intel_glk12eu_device = {
> + .max_compute_unit = 12,
> + .max_thread_per_unit = 6,
> + .sub_slice_count = 2,
> + .max_work_item_sizes = {512, 512, 512},
> + .max_work_group_size = 512,
> + .max_clock_frequency = 1000,
> +#include "cl_gen9_device.h"
> +};
> +
> LOCAL cl_device_id
> cl_get_gt_device(cl_device_type device_type) { @@ -737,6 +757,26 @@
> kbl_gt4_break:
> cl_intel_platform_enable_extension(ret, cl_khr_fp16_ext_id);
> break;
>
> + case PCI_CHIP_GLK_3x6:
> + DECL_INFO_STRING(glk18eu_break, intel_bxt18eu_device, name,
> +"Intel(R) HD Graphics Geminilake(3x6)");
> +glk18eu_break:
> + intel_glk18eu_device.device_id = device_id;
> + intel_glk18eu_device.platform = cl_get_platform_default();
> + ret = &intel_glk18eu_device;
> + cl_intel_platform_get_default_extension(ret);
> + cl_intel_platform_enable_extension(ret, cl_khr_fp16_ext_id);
> + break;
> +
> + case PCI_CHIP_GLK_2x6:
> + DECL_INFO_STRING(glk12eu_break, intel_bxt12eu_device, name,
> +"Intel(R) HD Graphics Geminilake(2x6)");
> +glk12eu_break:
> + intel_glk12eu_device.device_id = device_id;
> + intel_glk12eu_device.platform = cl_get_platform_default();
> + ret = &intel_glk12eu_device;
> + cl_intel_platform_get_default_extension(ret);
> + cl_intel_platform_enable_extension(ret, cl_khr_fp16_ext_id);
> + break;
> +
> case PCI_CHIP_SANDYBRIDGE_BRIDGE:
> case PCI_CHIP_SANDYBRIDGE_GT1:
> case PCI_CHIP_SANDYBRIDGE_GT2:
> @@ -942,7 +982,9 @@ LOCAL cl_bool is_gen_device(cl_device_id device) {
> device == &intel_kbl_gt15_device ||
> device == &intel_kbl_gt2_device ||
> device == &intel_kbl_gt3_device ||
> - device == &intel_kbl_gt4_device;
> + device == &intel_kbl_gt4_device ||
> + device == &intel_glk18eu_device ||
> + device == &intel_glk12eu_device;
> }
>
> LOCAL cl_int
> @@ -1365,7 +1407,8 @@ cl_device_get_version(cl_device_id device, cl_int
> *ver)
> || device == &intel_skl_gt3_device || device == &intel_skl_gt4_device
> || device == &intel_bxt18eu_device || device ==
> &intel_bxt12eu_device || device == &intel_kbl_gt1_device
> || device == &intel_kbl_gt2_device || device == &intel_kbl_gt3_device
> - || device == &intel_kbl_gt4_device || device ==
> &intel_kbl_gt15_device) {
> + || device == &intel_kbl_gt4_device || device ==
> &intel_kbl_gt15_device
> + || device == &intel_glk18eu_device || device ==
> + &intel_glk12eu_device) {
> *ver = 9;
> } else
> return CL_INVALID_VALUE;
> diff --git a/src/intel/intel_gpgpu.c b/src/intel/intel_gpgpu.c index
> 041938f..2b778e5 100644
> --- a/src/intel/intel_gpgpu.c
> +++ b/src/intel/intel_gpgpu.c
> @@ -2567,6 +2567,8 @@ intel_set_gpgpu_callbacks(int device_id)
> intel_gpgpu_get_scratch_index = intel_gpgpu_get_scratch_index_gen8;
> intel_gpgpu_post_action = intel_gpgpu_post_action_gen7; //SKL need
> not restore SLM, same as gen7
> intel_gpgpu_read_ts_reg = intel_gpgpu_read_ts_reg_gen7;
> + if(IS_GEMINILAKE(device_id))
> + intel_gpgpu_read_ts_reg = intel_gpgpu_read_ts_reg_baytrail;
> intel_gpgpu_set_base_address = intel_gpgpu_set_base_address_gen9;
> intel_gpgpu_setup_bti = intel_gpgpu_setup_bti_gen9;
> intel_gpgpu_load_vfe_state = intel_gpgpu_load_vfe_state_gen8;
> --
> 2.1.4
>
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