This set of drm patches implements support for 1D and 2D tiling on

[Alex Deucher]

First two patches enable scanout from tiled surfaces.
Third patch updates the CS checker to deal properly with tiling.
Fourth patch fixes surface checking for both tiled and non-tiled
pitch, height, and offset alignment.
Fifth patch adds a new info query for the MC tile config which is
required for CPU access to tiled surfaces.

To enable tiling, you need these drm patches as well as ddx and mesa
patches. On r6xx we expose 2 tiling modes 1D and 2D which map to the
MACRO and MICRO tiling flags we used on previous asics.  Unlike
previous asics, you cannot have macro tiled micro linear.

1D tiles are roughly equivalent to MICRO tiles on previous asics.
The 1D tile pattern is not dependant on the MC configuration.  2D
tiling is roughly equivalent to macro tiled micro tiled on previous
asics.  Macro tiles are made up of micro tiles and the macro tile
pattern is based on the MC configuration.

2D tiling should be used for optimal performance, however there are
some cases in the mesa de-tiling algorithm that don't work properly
yet with 2D tiling, so for now when you enable tiling in the ddx, it
will only enable 1D tiling.  To play with 2D tiling, select MACRO
rather then MICRO in radeon_dri2.c in the ddx.

Also, on r6xx/r7xx, we don't enable tiling of the front buffer as
that would require the use of wfb or tiled to untiled blits for CPU
access. Tiled to untiled blits works (I've tested it), but shows an
approximately 40% performance hit for software fallbacks (tested with
non-aa text in x11perf).  I'm not sure what how that compared to sw
detiling with wfb since the algo is pretty complex.  In practice, I
didn't notice any difference in performance on the desktop.

It might also be useful to benchmark using LINEAR_ALGINED rather than
LINEAR_GENERAL for linear surfaces as it is supposedly more efficient.

Alex