j.glisse at gmail.com
Fri Apr 15 09:11:28 PDT 2011
On Fri, Apr 15, 2011 at 11:46 AM, Joerg Roedel <joro at 8bytes.org> wrote:
> On Fri, Apr 15, 2011 at 03:16:50PM +0200, Ingo Molnar wrote:
>> Ok, but how did the allocation changes start triggering this error in
>> v2.6.39-rc1? There must still be some layout specific thing here, right?
>> Do we understand the details of that as well?
> Well, thinking again about this, the GPU likely generated this DMA
> request before too (which has an address in the range configured for the
> GTT on the card), but nobody noticed because they just hit main memory.
> And with the allocation changes in 39-rc1 the GART aperture started to
> be on the same address as the GTT (in their respective address spaces)
> so that the DMA request hit the GART. This caused the MCE and the
> The open question is why the GPU generates a DMA request with an address
> that is configured as the GTT base (+1 page) on the card.
Do you also got the write if you load radeon with radeon.no_wb=1 ?
I think at this address it's the wb page, or maybe the cp as wb likely
take only one page
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