[PATCH] Big endian support for RV730
Cédric Cano
ccano at interfaceconcept.com
Fri Feb 11 01:55:58 PST 2011
Signed-off-by: Cedric Cano <ccano at interfaceconcept.com>
---
diff -Naur xf86-video-ati-6.13.2/src/drmmode_display.c
xf86-video-ati-6.13.2/src/drmmode_display.c
--- xf86-video-ati-6.13.2/src/drmmode_display.c 2010-09-28
00:20:53.000000000 +0200
+++ xf86-video-ati-6.13.2/src/drmmode_display.c 2011-02-10
14:27:56.000000000 +0100
@@ -385,12 +385,15 @@
drmmode_load_cursor_argb (xf86CrtcPtr crtc, CARD32 *image)
{
drmmode_crtc_private_ptr drmmode_crtc = crtc->driver_private;
- void *ptr;
+ int i;
+ uint32_t *ptr;
/* cursor should be mapped already */
- ptr = drmmode_crtc->cursor_bo->ptr;
+ ptr = (uint32_t *)(drmmode_crtc->cursor_bo->ptr);
- memcpy (ptr, image, 64 * 64 * 4);
+ for(i = 0; i < 64 * 64; i++) {
+ ptr[i] = cpu_to_le32(image[i]);
+ }
return;
}
diff -Naur xf86-video-ati-6.13.2/src/r600_exa.c
xf86-video-ati-6.13.2/src/r600_exa.c
--- xf86-video-ati-6.13.2/src/r600_exa.c 2010-09-28
00:20:53.000000000 +0200
+++ xf86-video-ati-6.13.2/src/r600_exa.c 2011-02-10
14:29:03.000000000 +0100
@@ -247,9 +247,15 @@
} else if (accel_state->dst_obj.bpp == 16) {
cb_conf.format = COLOR_5_6_5;
cb_conf.comp_swap = 2; /* RGB */
+#if X_BYTE_ORDER == X_BIG_ENDIAN
+ cb_conf.endian = ENDIAN_8IN16;
+#endif
} else {
cb_conf.format = COLOR_8_8_8_8;
cb_conf.comp_swap = 1; /* ARGB */
+#if X_BYTE_ORDER == X_BIG_ENDIAN
+ cb_conf.endian = ENDIAN_8IN32;
+#endif
}
cb_conf.source_format = 1;
cb_conf.blend_clamp = 1;
@@ -942,7 +948,18 @@
tex_res.bo = accel_state->src_obj[unit].bo;
tex_res.mip_bo = accel_state->src_obj[unit].bo;
tex_res.request_size = 1;
-
+#if X_BYTE_ORDER == X_BIG_ENDIAN
+ switch(accel_state->src_obj[unit].bpp) {
+ case 16:
+ tex_res.endian = SQ_ENDIAN_8IN16;
+ break;
+ case 32:
+ tex_res.endian = SQ_ENDIAN_8IN32;
+ break;
+ default :
+ break;
+ }
+#endif
/* component swizzles */
switch (pPict->format) {
case PICT_a1r5g5b5:
@@ -1405,6 +1422,18 @@
}
cb_conf.source_format = 1;
cb_conf.blend_clamp = 1;
+#if X_BYTE_ORDER == X_BIG_ENDIAN
+ switch(dst_obj.bpp) {
+ case 16:
+ cb_conf.endian = ENDIAN_8IN16;
+ break;
+ case 32:
+ cb_conf.endian = ENDIAN_8IN32;
+ break;
+ default:
+ break;
+ }
+#endif
set_render_target(pScrn, accel_state->ib, &cb_conf,
accel_state->dst_obj.domain);
BEGIN_BATCH(24);
@@ -2116,6 +2145,15 @@
accel_state->xv_ps_offset = 3584;
R600_xv_ps(ChipSet, shader + accel_state->xv_ps_offset / 4);
+#if X_BYTE_ORDER == X_BIG_ENDIAN
+ {
+ int i;
+ for(i = 0; i < (4096 / 4); i++) {
+ shader[i] = cpu_to_le32(shader[i]);
+ }
+ }
+#endif
+
#ifdef XF86DRM_MODE
#if (EXA_VERSION_MAJOR == 2 && EXA_VERSION_MINOR >= 4)
if (info->cs) {
diff -Naur xf86-video-ati-6.13.2/src/r600_shader.c
xf86-video-ati-6.13.2/src/r600_shader.c
--- xf86-video-ati-6.13.2/src/r600_shader.c 2010-09-28
00:20:53.000000000 +0200
+++ xf86-video-ati-6.13.2/src/r600_shader.c 2011-02-10
14:30:10.000000000 +0100
@@ -111,7 +111,11 @@
FORMAT_COMP_ALL(SQ_FORMAT_COMP_SIGNED),
SRF_MODE_ALL(SRF_MODE_ZERO_CLAMP_MINUS_ONE));
shader[i++] = VTX_DWORD2(OFFSET(0),
- ENDIAN_SWAP(ENDIAN_NONE),
+#if X_BYTE_ORDER == X_BIG_ENDIAN
+ ENDIAN_SWAP(SQ_ENDIAN_8IN32),
+#else
+ ENDIAN_SWAP(SQ_ENDIAN_NONE),
+#endif
CONST_BUF_NO_STRIDE(0),
MEGA_FETCH(1));
shader[i++] = VTX_DWORD_PAD;
@@ -341,7 +345,11 @@
FORMAT_COMP_ALL(SQ_FORMAT_COMP_SIGNED),
SRF_MODE_ALL(SRF_MODE_ZERO_CLAMP_MINUS_ONE));
shader[i++] = VTX_DWORD2(OFFSET(0),
- ENDIAN_SWAP(ENDIAN_NONE),
+#if X_BYTE_ORDER == X_BIG_ENDIAN
+ ENDIAN_SWAP(SQ_ENDIAN_8IN32),
+#else
+ ENDIAN_SWAP(SQ_ENDIAN_NONE),
+#endif
CONST_BUF_NO_STRIDE(0),
MEGA_FETCH(1));
shader[i++] = VTX_DWORD_PAD;
@@ -366,7 +374,11 @@
FORMAT_COMP_ALL(SQ_FORMAT_COMP_SIGNED),
SRF_MODE_ALL(SRF_MODE_ZERO_CLAMP_MINUS_ONE));
shader[i++] = VTX_DWORD2(OFFSET(8),
- ENDIAN_SWAP(ENDIAN_NONE),
+#if X_BYTE_ORDER == X_BIG_ENDIAN
+ ENDIAN_SWAP(SQ_ENDIAN_8IN32),
+#else
+ ENDIAN_SWAP(SQ_ENDIAN_NONE),
+#endif
CONST_BUF_NO_STRIDE(0),
MEGA_FETCH(0));
shader[i++] = VTX_DWORD_PAD;
@@ -596,7 +608,11 @@
FORMAT_COMP_ALL(SQ_FORMAT_COMP_SIGNED),
SRF_MODE_ALL(SRF_MODE_ZERO_CLAMP_MINUS_ONE));
shader[i++] = VTX_DWORD2(OFFSET(0),
- ENDIAN_SWAP(ENDIAN_NONE),
+#if X_BYTE_ORDER == X_BIG_ENDIAN
+ ENDIAN_SWAP(SQ_ENDIAN_8IN32),
+#else
+ ENDIAN_SWAP(SQ_ENDIAN_NONE),
+#endif
CONST_BUF_NO_STRIDE(0),
MEGA_FETCH(1));
shader[i++] = VTX_DWORD_PAD;
@@ -621,7 +637,11 @@
FORMAT_COMP_ALL(SQ_FORMAT_COMP_SIGNED),
SRF_MODE_ALL(SRF_MODE_ZERO_CLAMP_MINUS_ONE));
shader[i++] = VTX_DWORD2(OFFSET(8),
- ENDIAN_SWAP(ENDIAN_NONE),
+#if X_BYTE_ORDER == X_BIG_ENDIAN
+ ENDIAN_SWAP(SQ_ENDIAN_8IN32),
+#else
+ ENDIAN_SWAP(SQ_ENDIAN_NONE),
+#endif
CONST_BUF_NO_STRIDE(0),
MEGA_FETCH(0));
shader[i++] = VTX_DWORD_PAD;
@@ -1813,7 +1833,11 @@
FORMAT_COMP_ALL(SQ_FORMAT_COMP_SIGNED),
SRF_MODE_ALL(SRF_MODE_ZERO_CLAMP_MINUS_ONE));
shader[i++] = VTX_DWORD2(OFFSET(0),
- ENDIAN_SWAP(ENDIAN_NONE),
+#if X_BYTE_ORDER == X_BIG_ENDIAN
+ ENDIAN_SWAP(SQ_ENDIAN_8IN32),
+#else
+ ENDIAN_SWAP(SQ_ENDIAN_NONE),
+#endif
CONST_BUF_NO_STRIDE(0),
MEGA_FETCH(1));
shader[i++] = VTX_DWORD_PAD;
@@ -1838,7 +1862,11 @@
FORMAT_COMP_ALL(SQ_FORMAT_COMP_SIGNED),
SRF_MODE_ALL(SRF_MODE_ZERO_CLAMP_MINUS_ONE));
shader[i++] = VTX_DWORD2(OFFSET(8),
- ENDIAN_SWAP(ENDIAN_NONE),
+#if X_BYTE_ORDER == X_BIG_ENDIAN
+ ENDIAN_SWAP(SQ_ENDIAN_8IN32),
+#else
+ ENDIAN_SWAP(SQ_ENDIAN_NONE),
+#endif
CONST_BUF_NO_STRIDE(0),
MEGA_FETCH(0));
shader[i++] = VTX_DWORD_PAD;
@@ -1863,7 +1891,11 @@
FORMAT_COMP_ALL(SQ_FORMAT_COMP_SIGNED),
SRF_MODE_ALL(SRF_MODE_ZERO_CLAMP_MINUS_ONE));
shader[i++] = VTX_DWORD2(OFFSET(16),
- ENDIAN_SWAP(ENDIAN_NONE),
+#if X_BYTE_ORDER == X_BIG_ENDIAN
+ ENDIAN_SWAP(SQ_ENDIAN_8IN32),
+#else
+ ENDIAN_SWAP(SQ_ENDIAN_NONE),
+#endif
CONST_BUF_NO_STRIDE(0),
MEGA_FETCH(0));
shader[i++] = VTX_DWORD_PAD;
@@ -1889,7 +1921,11 @@
FORMAT_COMP_ALL(SQ_FORMAT_COMP_SIGNED),
SRF_MODE_ALL(SRF_MODE_ZERO_CLAMP_MINUS_ONE));
shader[i++] = VTX_DWORD2(OFFSET(0),
- ENDIAN_SWAP(ENDIAN_NONE),
+#if X_BYTE_ORDER == X_BIG_ENDIAN
+ ENDIAN_SWAP(SQ_ENDIAN_8IN32),
+#else
+ ENDIAN_SWAP(SQ_ENDIAN_NONE),
+#endif
CONST_BUF_NO_STRIDE(0),
MEGA_FETCH(1));
shader[i++] = VTX_DWORD_PAD;
@@ -1914,7 +1950,11 @@
FORMAT_COMP_ALL(SQ_FORMAT_COMP_SIGNED),
SRF_MODE_ALL(SRF_MODE_ZERO_CLAMP_MINUS_ONE));
shader[i++] = VTX_DWORD2(OFFSET(8),
- ENDIAN_SWAP(ENDIAN_NONE),
+#if X_BYTE_ORDER == X_BIG_ENDIAN
+ ENDIAN_SWAP(SQ_ENDIAN_8IN32),
+#else
+ ENDIAN_SWAP(SQ_ENDIAN_NONE),
+#endif
CONST_BUF_NO_STRIDE(0),
MEGA_FETCH(0));
shader[i++] = VTX_DWORD_PAD;
diff -Naur xf86-video-ati-6.13.2/src/r600_textured_videofuncs.c
xf86-video-ati-6.13.2/src/r600_textured_videofuncs.c
--- xf86-video-ati-6.13.2/src/r600_textured_videofuncs.c 2010-09-28
00:20:53.000000000 +0200
+++ xf86-video-ati-6.13.2/src/r600_textured_videofuncs.c 2011-02-10
14:30:25.000000000 +0100
@@ -429,10 +429,16 @@
cb_conf.format = COLOR_5_6_5;
cb_conf.comp_swap = 2; /* RGB */
}
+#if X_BYTE_ORDER == X_BIG_ENDIAN
+ cb_conf.endian = ENDIAN_8IN16;
+#endif
break;
case 32:
cb_conf.format = COLOR_8_8_8_8;
cb_conf.comp_swap = 1; /* ARGB */
+#if X_BYTE_ORDER == X_BIG_ENDIAN
+ cb_conf.endian = ENDIAN_8IN32;
+#endif
break;
default:
return;
diff -Naur xf86-video-ati-6.13.2/src/r6xx_accel.c
xf86-video-ati-6.13.2/src/r6xx_accel.c
--- xf86-video-ati-6.13.2/src/r6xx_accel.c 2010-09-28
00:20:53.000000000 +0200
+++ xf86-video-ati-6.13.2/src/r6xx_accel.c 2011-02-08
11:46:29.000000000 +0100
@@ -1117,7 +1117,11 @@
BEGIN_BATCH(8 + count);
EREG(ib, VGT_PRIMITIVE_TYPE, draw_conf->prim_type);
PACK3(ib, IT_INDEX_TYPE, 1);
+#if X_BYTE_ORDER == X_BIG_ENDIAN
+ E32(ib, (2 << 2) | draw_conf->index_type);
+#else
E32(ib, draw_conf->index_type);
+#endif
PACK3(ib, IT_NUM_INSTANCES, 1);
E32(ib, draw_conf->num_instances);
@@ -1147,7 +1151,11 @@
BEGIN_BATCH(10);
EREG(ib, VGT_PRIMITIVE_TYPE, draw_conf->prim_type);
PACK3(ib, IT_INDEX_TYPE, 1);
+#if X_BYTE_ORDER == X_BIG_ENDIAN
+ E32(ib, (2 << 2) | draw_conf->index_type);
+#else
E32(ib, draw_conf->index_type);
+#endif
PACK3(ib, IT_NUM_INSTANCES, 1);
E32(ib, draw_conf->num_instances);
PACK3(ib, IT_DRAW_INDEX_AUTO, 2);
@@ -1183,6 +1191,9 @@
vtx_res.mem_req_size = 1;
vtx_res.vb_addr = accel_state->vb_mc_addr +
accel_state->vb_start_op;
vtx_res.bo = accel_state->vb_bo;
+#if X_BYTE_ORDER == X_BIG_ENDIAN
+ vtx_res.endian = SQ_ENDIAN_8IN32;
+#endif
set_vtx_resource (pScrn, accel_state->ib, &vtx_res,
RADEON_GEM_DOMAIN_GTT);
/* Draw */
diff -Naur xf86-video-ati-6.13.2/src/radeon_atombios.c
xf86-video-ati-6.13.2/src/radeon_atombios.c
--- xf86-video-ati-6.13.2/src/radeon_atombios.c 2010-09-28
00:20:53.000000000 +0200
+++ xf86-video-ati-6.13.2/src/radeon_atombios.c 2011-02-08
11:47:15.000000000 +0100
@@ -782,15 +782,15 @@
mode->CrtcHDisplay = mode->HDisplay = le16_to_cpu(dtd->usHActive);
mode->CrtcVDisplay = mode->VDisplay = le16_to_cpu(dtd->usVActive);
- mode->CrtcHBlankStart = dtd->usHActive + dtd->ucHBorder;
+ mode->CrtcHBlankStart = le16_to_cpu(dtd->usHActive) + dtd->ucHBorder;
mode->CrtcHBlankEnd = mode->CrtcHBlankStart +
le16_to_cpu(dtd->usHBlanking_Time);
mode->CrtcHTotal = mode->HTotal = mode->CrtcHBlankEnd +
dtd->ucHBorder;
- mode->CrtcVBlankStart = dtd->usVActive + dtd->ucVBorder;
+ mode->CrtcVBlankStart = le16_to_cpu(dtd->usVActive) + dtd->ucVBorder;
mode->CrtcVBlankEnd = mode->CrtcVBlankStart +
le16_to_cpu(dtd->usVBlanking_Time);
mode->CrtcVTotal = mode->VTotal = mode->CrtcVBlankEnd +
dtd->ucVBorder;
mode->CrtcHSyncStart = mode->HSyncStart = dtd->usHActive +
le16_to_cpu(dtd->usHSyncOffset);
mode->CrtcHSyncEnd = mode->HSyncEnd = mode->HSyncStart +
le16_to_cpu(dtd->usHSyncWidth);
- mode->CrtcVSyncStart = mode->VSyncStart = dtd->usVActive +
le16_to_cpu(dtd->usVSyncOffset);
+ mode->CrtcVSyncStart = mode->VSyncStart =
le16_to_cpu(dtd->usVActive) + le16_to_cpu(dtd->usVSyncOffset);
mode->CrtcVSyncEnd = mode->VSyncEnd = mode->VSyncStart +
le16_to_cpu(dtd->usVSyncWidth);
mode->SynthClock = mode->Clock = le16_to_cpu(dtd->usPixClk) * 10;
@@ -1541,7 +1541,7 @@
if (IS_DCE4_VARIANT) {
if ((i == 7) &&
- (gpio->usClkMaskRegisterIndex == 0x1936) &&
+ (le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x1936) &&
(gpio->sucI2cId.ucAccess == 0)) {
gpio->sucI2cId.ucAccess = 0x97;
gpio->ucDataMaskShift = 8;
@@ -1646,7 +1646,7 @@
for (i = 0; i < num_indices; i++) {
pin = &gpio_info->asGPIO_Pin[i];
if (record->ucHPDIntGPIOID == pin->ucGPIO_ID) {
- if ((pin->usGpioPin_AIndex * 4) == reg) {
+ if ((le16_to_cpu(pin->usGpioPin_AIndex) * 4) == reg) {
switch (pin->ucGpioPinBitShift) {
case 0:
default:
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