[Bug 29502] New: Change to legacy algo to preferring lower post dividers breaks certain modelines
bugzilla-daemon at bugzilla.kernel.org
bugzilla-daemon at bugzilla.kernel.org
Sat Feb 19 18:29:32 PST 2011
https://bugzilla.kernel.org/show_bug.cgi?id=29502
Summary: Change to legacy algo to preferring lower post
dividers breaks certain modelines
Product: Drivers
Version: 2.5
Kernel Version: 2.6.38-rc5
Platform: All
OS/Version: Linux
Tree: Mainline
Status: NEW
Severity: normal
Priority: P1
Component: Video(DRI - non Intel)
AssignedTo: drivers_video-dri at kernel-bugs.osdl.org
ReportedBy: bitbytebit at gmail.com
Regression: Yes
There's an issue with some legacy chips plus low dotclocks in the 2.6.38-rc5
kernel, This is the change/patch that broke them. Reverting this patch, they
work as they did before...
"Also, switch the legacy algo back to preferring lower post dividers."
@@ -849,7 +951,7 @@ void radeon_compute_pll(struct radeon_pll *pll,
max_fractional_feed_div = pll->max_frac_feedback_div;
}
- for (post_div = max_post_div; post_div >= min_post_div; --post_div) {
+ for (post_div = min_post_div; post_div <= max_post_div; ++post_div) {
uint32_t ref_div;
if ((pll->flags & RADEON_PLL_NO_ODD_POST_DIV) && (post_div & 1))
A person has a ATI Radeon 9200SE 5964 (AGP)and with 2.6.38-rc4-git4+ it works
while with 2.6.38-rc5 there are certain (not all) modelines with low dotclocks
that end up being totally out of sync.
Here's an example of a non-working modeline for him with the newer kernel, vs.
the older one step back before the patch with the above change...
# toki 256x224 at 59.61 15.6774Khz
ModeLine "256x224x59.61" 5.518455 256 272 304 352 224 235 238 263
-HSync -VSync
There's a lot of other ones thought that can work with the same lower
dotclocks, so I'm not sure why that is, he tested that change with the legacy
pll computation reversed back to how it was and now works again with modelines
like the above.
Thanks,
Chris
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