[Bug 48880] Set mode has different timings than requested on VGA

bugzilla-daemon at freedesktop.org bugzilla-daemon at freedesktop.org
Wed Apr 18 12:22:55 PDT 2012


--- Comment #10 from Alex Deucher <agd5f at yahoo.com> 2012-04-18 12:22:55 PDT ---
Is it only problematic on VGA or TMDS?  I.e., does one only one or the other,
but not both?  It seems to be something specific to your monitor.  I can't
reproduce this on my ontario hardware or monitors.  I manually added the
modeline you were using and it works fine here.  Can you try slightly different
timing?  Some monitors are really picky about the clocks and sometimes they do
not like certain pll divider combinations even though the result is the the
same clock.  You might try setting the  RADEON_PLL_PREFER_MINM_OVER_MAXP or
RADEON_PLL_USE_FRAC_FB_DIV pll flags in atombios_adjust_pll() and see if either
of those helps.

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