[Bug 48880] Set mode has different timings than requested on VGA

bugzilla-daemon at freedesktop.org bugzilla-daemon at freedesktop.org
Thu Apr 19 07:02:28 PDT 2012


--- Comment #19 from Alex Deucher <agd5f at yahoo.com> 2012-04-19 07:02:28 PDT ---
(In reply to comment #18)
> (In reply to comment #15)
> > 
> > Err, Alex, i think that it is the display engine, for a particular version and
> > process, that has issues with certain divider combinations which should
> > theoretically produce the same pixel clock, not the monitor.
> I'm not so sure about that.  If I use the same divider combination on my
> monitors, it works fine (both TMDS and analog).  It even works fine for Tvrtko
> over TMDS.  It's possible the that due to a cable problem or a bad solder
> inside that the pixel clock that eventually gets to the screen is in some cases
> is too low and boosting the pixel clock slightly compensates for that.

In really it's probably a combination of both.  Some pll divider combinations
are more stable than others and some monitors are less picky.

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