[PATCH] uxa: Align tiled surface size to an number of tiled rows

[Chris Wilson]

Align surface sizes to an even number of tile rows to cater for sampler
prefetch, as shown by enabling GPU invalid PTE detection (i.e. clearing
the valid bit of the PTE).
---

We are investigating bug
https://bugs.freedesktop.org/show_bug.cgi?id=55984 where the only lead
so far is the ordering of eviction under memory pressure. This patch
seems promising because the GPU is detecting that we are accessing invalid
pages beyond the end of our allocations (and so the eviction may lead us
to randomly read the scratch PTE and randomly hang the GPU), however the
only bug that I have seen with such a tell-tale error state is
https://bugzilla.redhat.com/show_bug.cgi?id=877461
-Chris

---
 src/intel_uxa.c |    2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/intel_uxa.c b/src/intel_uxa.c
index f5ac0a6..2f14173 100644
--- a/src/intel_uxa.c
+++ b/src/intel_uxa.c
@@ -209,7 +209,7 @@ intel_uxa_pixmap_compute_size(PixmapPtr pixmap,
 			tile_height = 8;
 		else
 			tile_height = 32;
-		aligned_h = ALIGN(h, tile_height);
+		aligned_h = ALIGN(h, 2*tile_height);
 
 		*stride = intel_get_fence_pitch(intel,
 						ALIGN(pitch, 512),
-- 
1.7.10.4