R600 definition error for interrupt handler swap

[Alex Deucher]

On Wed, Feb 1, 2012 at 4:33 AM, Cédric Cano <ccano at interfaceconcept.com> wrote:
> Hello,
>
> We're trying to use R600 DRM driver with big endian architecture. We find
> the following error in R600 definition of interrupt handler swap.
>
> Perhaps there's the same error in the evergreen definitions header file.

The definition in the register header is correct according to the
register spec.  It's bits 2:1 on both r6xx and evergreen.

0 = no swap
1 = 16 bit swap (0xaabb becomes 0xbbaa)
2 = 32 bit swap (0xaabbccdd becomes 0xddccbbaa)
3 = 64 bit swap (0xaabbccddeeff0011 becomes 0x1100ffeeddccbbaa))

Alex

>
> Cedric
>
> Signed-off-by: Cédric Cano <ccano at interfaceconcept.com>
> Signed-off-by: Thomas Jourdan <tjourdan at interfaceconcept.com>
> ---
> diff -Naur linux-3.2.2/drivers/gpu/drm/radeon/r600d.h
> linux-3.2.2/drivers/gpu/drm/radeon/r600d.h
> --- linux-3.2.2/drivers/gpu/drm/radeon/r600d.h    2012-01-26
> 01:39:32.000000000 +0100
> +++ linux-3.2.2/drivers/gpu/drm/radeon/r600d.h    2012-02-01
> 10:25:04.000000000 +0100
> @@ -552,7 +552,7 @@
>  #define IH_RB_WPTR_ADDR_LO                                0x3e14
>  #define IH_CNTL                                           0x3e18
>  #       define ENABLE_INTR                                (1 << 0)
> -#       define IH_MC_SWAP(x)                              ((x) << 1)
> +#       define IH_MC_SWAP(x)                              ((x) << 2)
>  #       define IH_MC_SWAP_NONE                            0
>  #       define IH_MC_SWAP_16BIT                           1
>  #       define IH_MC_SWAP_32BIT                           2
> --
>
>
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