[PATCH 1/2] drm/radeon: add some additional 6xx/7xx/EG register init

[Michel Dänzer]

On Don, 2012-06-14 at 22:06 +0200, Marek Olšák wrote: 
> From: Alex Deucher <alexander.deucher at amd.com>
> 
> - SMX_SAR_CTL0 needs to be programmed correctly to prevent
> problems with memory exports in certain cases.
> - VC_ENHANCE needs to be initialized on 6xx/7xx.
> 
> Signed-off-by: Alex Deucher <alexander.deucher at amd.com>
> Cc: stable at vger.kernel.org
> ---
>  drivers/gpu/drm/radeon/evergreen.c  |    3 +++
>  drivers/gpu/drm/radeon/evergreend.h |    1 +
>  drivers/gpu/drm/radeon/r600.c       |    1 +
>  drivers/gpu/drm/radeon/r600d.h      |    1 +
>  drivers/gpu/drm/radeon/rv770.c      |    5 ++++-
>  drivers/gpu/drm/radeon/rv770d.h     |    3 +++
>  6 files changed, 13 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/radeon/evergreen.c b/drivers/gpu/drm/radeon/evergreen.c
> index 01550d0..7fb3d2e 100644
> --- a/drivers/gpu/drm/radeon/evergreen.c
> +++ b/drivers/gpu/drm/radeon/evergreen.c
> @@ -1932,6 +1932,9 @@ static void evergreen_gpu_init(struct radeon_device *rdev)
>  	smx_dc_ctl0 |= NUMBER_OF_SETS(rdev->config.evergreen.sx_num_of_sets);
>  	WREG32(SMX_DC_CTL0, smx_dc_ctl0);
>  
> +	if (rdev->family <= CHIP_SUMO2)
> +		WREG32(SMX_SAR_CTL0, 0x00010000);
> +

What about later generations? AFAICT Cayman (and thus maybe also Aruba)
still has this register.


-- 
Earthling Michel Dänzer           |                   http://www.amd.com
Libre software enthusiast         |          Debian, X and DRI developer