[PATCH 2/2] drm/radeon: Restrict offset for legacy display engine.

[Alex Deucher]

2012/3/14 Michel Dänzer <michel at daenzer.net>:
> From: Michel Dänzer <michel.daenzer at amd.com>
>
> The hardware only takes 27 bits for the offset, so larger offsets are
> truncated, and the display shows random bits other than the intended ones.
>
> Signed-off-by: Michel Dänzer <michel.daenzer at amd.com>

Reviewed-by: Alex Deucher <alexander.deucher at amd.com>

This should probably go to stable as well.  I think it may also fix this bug:
https://bugzilla.kernel.org/show_bug.cgi?id=16515

Alex

> ---
>  drivers/gpu/drm/radeon/radeon_display.c     |    4 +++-
>  drivers/gpu/drm/radeon/radeon_fb.c          |    5 ++++-
>  drivers/gpu/drm/radeon/radeon_legacy_crtc.c |    4 +++-
>  3 files changed, 10 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/radeon/radeon_display.c b/drivers/gpu/drm/radeon/radeon_display.c
> index d3ffc18..63386a4 100644
> --- a/drivers/gpu/drm/radeon/radeon_display.c
> +++ b/drivers/gpu/drm/radeon/radeon_display.c
> @@ -393,7 +393,9 @@ static int radeon_crtc_page_flip(struct drm_crtc *crtc,
>                DRM_ERROR("failed to reserve new rbo buffer before flip\n");
>                goto pflip_cleanup;
>        }
> -       r = radeon_bo_pin(rbo, RADEON_GEM_DOMAIN_VRAM, &base);
> +       /* Only 27 bit offset for legacy CRTC */
> +       r = radeon_bo_pin_restricted(rbo, RADEON_GEM_DOMAIN_VRAM,
> +                                    ASIC_IS_AVIVO(rdev) ? 0 : 1 << 27, &base);
>        if (unlikely(r != 0)) {
>                radeon_bo_unreserve(rbo);
>                r = -EINVAL;
> diff --git a/drivers/gpu/drm/radeon/radeon_fb.c b/drivers/gpu/drm/radeon/radeon_fb.c
> index cf2bf35..93bf920 100644
> --- a/drivers/gpu/drm/radeon/radeon_fb.c
> +++ b/drivers/gpu/drm/radeon/radeon_fb.c
> @@ -164,7 +164,10 @@ static int radeonfb_create_pinned_object(struct radeon_fbdev *rfbdev,
>        ret = radeon_bo_reserve(rbo, false);
>        if (unlikely(ret != 0))
>                goto out_unref;
> -       ret = radeon_bo_pin(rbo, RADEON_GEM_DOMAIN_VRAM, NULL);
> +       /* Only 27 bit offset for legacy CRTC */
> +       ret = radeon_bo_pin_restricted(rbo, RADEON_GEM_DOMAIN_VRAM,
> +                                      ASIC_IS_AVIVO(rdev) ? 0 : 1 << 27,
> +                                      NULL);
>        if (ret) {
>                radeon_bo_unreserve(rbo);
>                goto out_unref;
> diff --git a/drivers/gpu/drm/radeon/radeon_legacy_crtc.c b/drivers/gpu/drm/radeon/radeon_legacy_crtc.c
> index 25a19c4..210317c 100644
> --- a/drivers/gpu/drm/radeon/radeon_legacy_crtc.c
> +++ b/drivers/gpu/drm/radeon/radeon_legacy_crtc.c
> @@ -419,7 +419,9 @@ int radeon_crtc_do_set_base(struct drm_crtc *crtc,
>        r = radeon_bo_reserve(rbo, false);
>        if (unlikely(r != 0))
>                return r;
> -       r = radeon_bo_pin(rbo, RADEON_GEM_DOMAIN_VRAM, &base);
> +       /* Only 27 bit offset for legacy CRTC */
> +       r = radeon_bo_pin_restricted(rbo, RADEON_GEM_DOMAIN_VRAM, 1 << 27,
> +                                    &base);
>        if (unlikely(r != 0)) {
>                radeon_bo_unreserve(rbo);
>                return -EINVAL;
> --
> 1.7.9.1
>
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