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when the corresponding pins are not actually hooked up to anything.  In
these cases, there is no NAK, nor timeout, nor any other indication from
the GMBUS controller that a transaction fails.  The first gmbus
transaction timeout is caught by the "wait_for" timeout, causing the
transition to bit-banging mode for subsequent (failed) attempts.

This might be what was meant by the following note in the GPIO_CTL
description:
  "The registers that control digital display (HDMI/DVI, DisplayPort)
pins should only be utilized if the Port Detected bit in the related
control register is set to 1."
(http://intellinuxgraphics.org/documentation/SNB/IHD_OS_Vol3_Part3.pdf,
section 2.2.2)

Signed-off-by: Daniel Kurtz <djkurtz at chromium.org>
---
 drivers/gpu/drm/i915/intel_i2c.c |   10 +++++-----
 1 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_i2c.c b/drivers/gpu/drm/i915/intel_i2c.c
index 73431ed..154fedd 100644
--- a/drivers/gpu/drm/i915/intel_i2c.c
+++ b/drivers/gpu/drm/i915/intel_i2c.c
@@ -380,8 +380,8 @@ gmbus_xfer(struct i2c_adapter *adapter,
 	 */
 	if (wait_for((I915_READ(GMBUS2 + reg_offset) & GMBUS_ACTIVE) == 0,
 		     10)) {
-		DRM_INFO("GMBUS [%s] timed out waiting for idle\n",
-			 adapter->name);
+		DRM_ERROR("GMBUS [%s] timed out waiting for idle\n",
+			  adapter->name);
 		ret = -ETIMEDOUT;
 	}
 	I915_WRITE(GMBUS0 + reg_offset, 0);
@@ -396,7 +396,7 @@ clear_err:
 	 */
 	if (wait_for((I915_READ(GMBUS2 + reg_offset) & GMBUS_ACTIVE) == 0,
 		     10))
-		DRM_INFO("GMBUS [%s] timed out after NAK\n", adapter->name);
+		DRM_ERROR("GMBUS [%s] timed out after NAK\n", adapter->name);
 
 	/* Toggle the Software Clear Interrupt bit. This has the effect
 	 * of resetting the GMBUS controller and so clearing the
@@ -421,8 +421,8 @@ clear_err:
 	goto out;
 
 timeout:
-	DRM_INFO("GMBUS [%s] timed out, falling back to bit banging on pin %d\n",
-		 bus->adapter.name, bus->reg0 & 0xff);
+	DRM_ERROR("GMBUS [%s] timed out, falling back to bit banging on pin %d\n",
+		  bus->adapter.name, bus->reg0 & 0xff);
 	I915_WRITE(GMBUS0 + reg_offset, 0);
 
 	/* Hardware may not support GMBUS over these pins? Try GPIO bitbanging instead. */
-- 
1.7.7.3