[Linaro-mm-sig] A few questions about the best way to implement RandR 1.4 / PRIME buffer sharing

[Daniel Vetter]

On Tue, Sep 04, 2012 at 01:57:32PM -0700, Aaron Plattner wrote:
> On 08/31/2012 08:00 PM, Dave Airlie wrote:
> >Yes for 4 some sort of fencing is being worked on by Maarten for other stuff
> >but would be a pre-req for doing this, and also some devices don't want
> >fullscreen updates, like USB, so doing flipped updates would have to be
> >optional or negoitated. It makes sense for us as well since things like
> >gnome-shell can do full screen pageflips and we have to do full screen dirty
> >updates.
> 
> Right now my implementation has two sources of tearing:
> 
> 1. The dGPU reads the vidmem primary surface asynchronously from its own
>    rendering to it.
> 
> 2. The iGPU fetches the shared surface for display asynchronously from the dGPU
>    writing into it.
> 
> #1 I can fix within our driver.  For #2, I don't want to rely on the dGPU being
> able to push complete frames over the bus during vblank in response to an iGPU
> fence trigger so I was thinking we would want double-buffering all the time.
> Also, I was hoping to set up a proper flip chain between the dGPU, the dGPU's
> DMA engine, and the Intel display engine so that for full-screen applications,
> glXSwapBuffers is stalled properly without relying on the CPU to schedule
> things.  Maybe that's overly ambitious for now?

For the frontbuffer tearing Chris Wilson added a special mode to the SNA
intel driver that uses pageflips for all buffer updates (like windowized
Xv or dri2copybuffers), mostly because vsync'ed blits are busted on snb
(and not yet proved to be fixed on ivb). So we could use that mode for an
optimus platform.

Wrt the full flip-chain, that's what Maarten Lankhorst has running in his
proof-of-concept (but only for a second or so, since nouveau is totally
bust on his machine). The only place he wakes up the cpu is to sync from
nv to intel, but even there we can kick of the intel gpu directly from the
nv irq handler (with a simple register write). intel -> nv sync uses
memory based sequence numbers. Only proof of concept for rendering though,
iirc the fence support isn't wired up with the pageflipping on the intel
side yet.
-Daniel
-- 
Daniel Vetter
Mail: daniel at ffwll.ch
Mobile: +41 (0)79 365 57 48