[PATCH 2/3] drm/radeon: clean up audio dto programming

[Rafał Miłecki]

2013/4/19 Alex Deucher <alexdeucher at gmail.com>:
> On Fri, Apr 19, 2013 at 2:10 AM, Rafał Miłecki <zajec5 at gmail.com> wrote:
>> 2013/4/18  <alexdeucher at gmail.com>:
>>> -       switch (radeon_encoder->encoder_id) {
>>> -       case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
>>> -       case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
>>> -               WREG32_P(R600_AUDIO_TIMING, 0, ~0x301);
>>> -               break;
>>> -       case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
>>> -       case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
>>> -       case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
>>> -       case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
>>> -               WREG32_P(R600_AUDIO_TIMING, 0x100, ~0x301);
>>> -               break;
>>> -       default:
>>> -               dev_err(rdev->dev, "Unsupported encoder type 0x%02X\n",
>>> -                         radeon_encoder->encoder_id);
>>> -               return;
>>> -       }
>>
>> Are you sure we can just drop that part?
>
> Yes we should be able to drop that part.  The only relevant bits are
> 9:8 which allows you to force which DTO is used by the audio block.  0
> = auto, 1 = force dto0, 2 = force dto1.  Additionally, that register
> doesn't exist on evergreen and newer.  On evergreen and newer there is
> a DIG PHY register at the same offset which may explain the display
> problems some people are experiencing.

For now I can only say that fglrx seems to be changing that 0x7344:

RREG32(0x00000534); -> 0x00000001	DCCG_AUDIO_DTO_SELECT
WREG32(0x00000534, 0x00000000);		DCCG_AUDIO_DTO_SELECT

RREG32(0x00007344); -> 0x00000270
WREG32(0x00007344, 0x00000170);

RREG32(0x00000518); -> 0x00000000	DCCG_AUDIO_DTO0_MODULE
WREG32(0x00000518, 0x00e297d0);		DCCG_AUDIO_DTO0_MODULE
RREG32(0x00000514); -> 0x00000000	DCCG_AUDIO_DTO0_PHASE
WREG32(0x00000514, 0x00249f00);		DCCG_AUDIO_DTO0_PHASE

I can't say how well radeon is going to work without that, just
informing you about fglrx.

-- 
Rafał