[PATCH] drm/radeon: fix scratch reg handling for UVD fence

[Dieter Nützel]

Am 2013-04-24 14:12, schrieb Christian König:
> From: Christian König <christian.koenig at amd.com>
> 
> Also init the scratch reg to zero on the UVD ring.
> This fixes UVD on AGP based cards.
> 
> Signed-off-by: Christian König <christian.koenig at amd.com>

Tested-by: Dieter Nützel <dieter at nuetzel-hh.de>

RV730 AGP (UVD 2.2) works with radeon.agpmode=8, now.

[   10.394741] ATOM BIOS: 113
[   10.394948] [drm] AGP mode requested: 8
[   10.394960] agpgart-via 0000:00:00.0: AGP 3.5 bridge
[   10.394989] agpgart-via 0000:00:00.0: putting AGP V3 device into 8x 
mode
[   10.396634] radeon 0000:01:00.0: putting AGP V3 device into 8x mode
[   10.396649] radeon 0000:01:00.0: GTT: 256M 0xE0000000 - 0xEFFFFFFF
[   10.396661] radeon 0000:01:00.0: VRAM: 1024M 0xA0000000 - 0xDFFFFFFF 
(1024M used)
[   10.399244] [drm] Detected VRAM RAM=1024M, BAR=256M
[   10.399254] [drm] RAM width 128bits DDR
[   10.402125] [TTM] Zone  kernel: Available graphics memory: 441924 kiB
[   10.402133] [TTM] Zone highmem: Available graphics memory: 1033768 
kiB
[   10.402136] [TTM] Initializing pool allocator
[   10.402198] [drm] radeon: 1024M of VRAM memory ready
[   10.402202] [drm] radeon: 256M of GTT memory ready.
[   10.402244] [drm] Supports vblank timestamp caching Rev 1 
(10.10.2010).
[   10.402247] [drm] Driver supports precise vblank timestamp query.
[   10.402319] [drm] radeon: irq initialized.

[-]

[   10.524045] [drm] GART: num cpu pages 65536, num gpu pages 65536
[   10.528182] [drm] Loading RV730 Microcode
[   10.641945] radeon 0000:01:00.0: WB disabled
[   10.641964] radeon 0000:01:00.0: fence driver on ring 0 use gpu addr 
0x00000000e0000004 and cpu a
ddr 0xf84c0004
[   10.641969] radeon 0000:01:00.0: fence driver on ring 3 use gpu addr 
0x00000000e0000c0c and cpu addr 0xf84c0c0c
[   10.642218] radeon 0000:01:00.0: fence driver on ring 5 use gpu addr 
0x00000000a005c598 and cpu addr 0xf879c598
[   10.785565] [drm] ring test on 0 succeeded in 1 usecs
[   10.785636] [drm] ring test on 3 succeeded in 1 usecs
[   10.842237]  md127:
[   10.847965] [drm] ring test on 5 succeeded in 1 usecs
[   10.847976] [drm] UVD initialized successfully.
[   10.848690] [drm] ib test on ring 0 succeeded in 0 usecs
[   10.848729] [drm] ib test on ring 3 succeeded in 1 usecs
[   10.858255] [drm] ib test on ring 5 succeeded

Thank you Christian!

Dieter

> ---
> drivers/gpu/drm/radeon/radeon_fence.c |    2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/radeon/radeon_fence.c
> b/drivers/gpu/drm/radeon/radeon_fence.c
> index 1a699ce..5b937df 100644
> --- a/drivers/gpu/drm/radeon/radeon_fence.c
> +++ b/drivers/gpu/drm/radeon/radeon_fence.c
> @@ -767,8 +767,8 @@ int radeon_fence_driver_start_ring(struct
> radeon_device *rdev, int ring)
> 
> 	radeon_scratch_free(rdev, rdev->fence_drv[ring].scratch_reg);
> 	if (rdev->wb.use_event || !radeon_ring_supports_scratch_reg(rdev,
> &rdev->ring[ring])) {
> +		rdev->fence_drv[ring].scratch_reg = 0;
> 		if (ring != R600_RING_TYPE_UVD_INDEX) {
> -			rdev->fence_drv[ring].scratch_reg = 0;
> 			index = R600_WB_EVENT_OFFSET + ring * 4;
> 			rdev->fence_drv[ring].cpu_addr = &rdev->wb.wb[index/4];
> 			rdev->fence_drv[ring].gpu_addr = rdev->wb.gpu_addr +