[PATCH] drm/exynos: Replace mdelay with usleep_range

Inki Dae inki.dae at samsung.com
Tue Jan 15 18:07:24 PST 2013


Applied.

Thanks,
Inki Dae

2013/1/15 Sean Paul <seanpaul at chromium.org>:
> Replace the unnecessary atomic mdelay calls with usleep_range calls.
>
> Signed-off-by: Sean Paul <seanpaul at chromium.org>
> ---
>  drivers/gpu/drm/exynos/exynos_hdmi.c  |   14 +++++++-------
>  drivers/gpu/drm/exynos/exynos_mixer.c |    2 +-
>  2 files changed, 8 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/exynos/exynos_hdmi.c b/drivers/gpu/drm/exynos/exynos_hdmi.c
> index b2f8de9..4cf01f3 100644
> --- a/drivers/gpu/drm/exynos/exynos_hdmi.c
> +++ b/drivers/gpu/drm/exynos/exynos_hdmi.c
> @@ -1646,9 +1646,9 @@ static void hdmi_conf_reset(struct hdmi_context *hdata)
>
>         /* resetting HDMI core */
>         hdmi_reg_writemask(hdata, reg,  0, HDMI_CORE_SW_RSTOUT);
> -       mdelay(10);
> +       usleep_range(10000, 12000);
>         hdmi_reg_writemask(hdata, reg, ~0, HDMI_CORE_SW_RSTOUT);
> -       mdelay(10);
> +       usleep_range(10000, 12000);
>  }
>
>  static void hdmi_conf_init(struct hdmi_context *hdata)
> @@ -1773,7 +1773,7 @@ static void hdmi_v13_timing_apply(struct hdmi_context *hdata)
>                 u32 val = hdmi_reg_read(hdata, HDMI_V13_PHY_STATUS);
>                 if (val & HDMI_PHY_STATUS_READY)
>                         break;
> -               mdelay(1);
> +               usleep_range(1000, 2000);
>         }
>         /* steady state not achieved */
>         if (tries == 0) {
> @@ -1940,7 +1940,7 @@ static void hdmi_v14_timing_apply(struct hdmi_context *hdata)
>                 u32 val = hdmi_reg_read(hdata, HDMI_PHY_STATUS_0);
>                 if (val & HDMI_PHY_STATUS_READY)
>                         break;
> -               mdelay(1);
> +               usleep_range(1000, 2000);
>         }
>         /* steady state not achieved */
>         if (tries == 0) {
> @@ -1992,9 +1992,9 @@ static void hdmiphy_conf_reset(struct hdmi_context *hdata)
>
>         /* reset hdmiphy */
>         hdmi_reg_writemask(hdata, reg, ~0, HDMI_PHY_SW_RSTOUT);
> -       mdelay(10);
> +       usleep_range(10000, 12000);
>         hdmi_reg_writemask(hdata, reg,  0, HDMI_PHY_SW_RSTOUT);
> -       mdelay(10);
> +       usleep_range(10000, 12000);
>  }
>
>  static void hdmiphy_poweron(struct hdmi_context *hdata)
> @@ -2042,7 +2042,7 @@ static void hdmiphy_conf_apply(struct hdmi_context *hdata)
>                 return;
>         }
>
> -       mdelay(10);
> +       usleep_range(10000, 12000);
>
>         /* operation mode */
>         operation[0] = 0x1f;
> diff --git a/drivers/gpu/drm/exynos/exynos_mixer.c b/drivers/gpu/drm/exynos/exynos_mixer.c
> index e9dbf79..2be9833 100644
> --- a/drivers/gpu/drm/exynos/exynos_mixer.c
> +++ b/drivers/gpu/drm/exynos/exynos_mixer.c
> @@ -600,7 +600,7 @@ static void vp_win_reset(struct mixer_context *ctx)
>                 /* waiting until VP_SRESET_PROCESSING is 0 */
>                 if (~vp_reg_read(res, VP_SRESET) & VP_SRESET_PROCESSING)
>                         break;
> -               mdelay(10);
> +               usleep_range(10000, 12000);
>         }
>         WARN(tries == 0, "failed to reset Video Processor\n");
>  }
> --
> 1.7.7.3
>
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