[PATCH] drm: fix to radeon driver for HD 6450

[Alex Deucher]

On Fri, Jan 25, 2013 at 1:10 PM, Chris Staite <chris at yourdreamnet.co.uk> wrote:
> From: Christopher Staite <chris at yourdreamnet.co.uk>
>
> Fix commit 62444b7462a2b98bc78d68736c03a7c4e66ba7e2 for HD 6450.  The stop and resume causes the screen to glitch and the X server to reboot constantly.  Re-instating the UPDATE_LOCK fixes the issue in tests on the v3.6.11 stable, and the code has not been altered to fix this since.
>
> Signed-off-by: Christopher Staite <chris at yourdreamnet.co.uk>
>

Looks good.  I've updated the patch to handle the DCE6 case and
improved the commit message.  I'll go ahead and add it to my next
-fixes pull.

Thanks,

Alex

>
>
> --- drivers/gpu/drm/radeon/evergreen.c.org      2013-01-25 17:45:06.000000000 +0000
> +++ drivers/gpu/drm/radeon/evergreen.c  2013-01-25 17:48:14.000000000 +0000
> @@ -1320,7 +1320,9 @@ void evergreen_mc_stop(struct radeon_dev
>                                 if (!(tmp & EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE)) {
>                                         radeon_wait_for_vblank(rdev, i);
>                                         tmp |= EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE;
> +                                       WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 1);
>                                         WREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i], tmp);
> +                                       WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 0);
>                                 }
>                         }
>                         /* wait for the next frame */
> @@ -1382,7 +1384,9 @@ void evergreen_mc_resume(struct radeon_d
>                         } else {
>                                 tmp = RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i]);
>                                 tmp &= ~EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE;
> +                               WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 1);
>                                 WREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i], tmp);
> +                               WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 0);
>                         }
>                         /* wait for the next frame */
>                         frame_count = radeon_get_vblank_counter(rdev, i);
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